Abstract: A modified partitioning method for placement of a circuit design into a programmable integrated circuit device (PICD), the PICD having a specific distribution of physical resources corresponding to a specific circuit structure. The circuit design includes a plurality of circuit elements which include specific circuit elements which correspond to the specific circuit structure. The modified method includes the steps of identifying the specific circuit elements and partitioning the plurality of circuit elements such that the identified specific circuit elements are placed in a location corresponding to the specific physical distribution of resources.

Abstract: A capacitor is formed in three adjacent conductive layers of a semiconductor integrated circuit chip. A first plate of the capacitor is formed in the middle layer. A second plate is formed in the upper and lower layers plus a small portion of the middle layer which interconnects the upper and lower layers and forms a U-shaped structure surrounding the first plate. These capacitors are preferably formed in pairs with the first plates interconnected. The second plates may be connected to different voltage supplies to form a capacitive voltage divider.

Abstract: The integrity of a circuit processing logic signals is verified by use of switching means, including pass transistors, which are selectively varied to provide different test circuit configurations for different modes of operation. The circuit operates in normal, scan, test and data receive modes. During normal operation, the logic signal from the primary circuit is passed directly through a logic test block without the shifting of data in the logic test block.

Abstract: A five transistor memory cell that can be reliably read and written from a single data line. The cell includes two inverters and a pass transistor. The cell read/write circuitry includes an address supply voltage source which is maintained at a first level during write and at a second level during read, selected to reduce read disturbance. The memory cell read circuitry includes a circuit for precharging the cell data line prior to reading. The state of the memory cell is continuously available at output nodes to control other circuitry even during the read operation. Selective doping of the pull-up transistors of the inverters in the memory cell controls the initial state of the memory cell after the memory cell is powered up.

Abstract: A structure especially useful in a configurable logic array includes a plurality of conductive interconnect lines located along the perimeter of a logic array chip. Lines running from exterior pins or pads can be used by a programmable interconnect circuit to control signals applied to these interconnect lines. In particular, both the signal and the complement of the signal can be used by the programmable interconnect to control application of a supply voltage to an interconnect line. A second supply voltage is applied through a resistor to the interconnect line with the result that the interconnect line will carry a logical signal representing a logical function, for example AND, of a selected set of input signals or their complements. Lines running from points interior to the configurable logic array chip may also contribute to the signal generated on an interconnect line. In one embodiment, bidirectional programmable interconnect circuits allow the input pins to function as either input or output pins.

Abstract: A structure and method for producing mask-configured integrated circuits which are pin compatible substitutes for user-configured logic arrays is disclosed. Mask-defined routing lines having resistive/capacitive characteristics simulating those of user-configurable routing paths in the user-configurable logic array are used in the mask-defined substitutes to replace the user-configurable routing paths. Scan testing networks are formed in the metal-configured substitutes to test the operability of logical function blocks formed on such chips. The scan testing networks comprise a plurality of test blocks each including three field effect pass transistors formed of four adjacent diffusion regions. Proper connection of the gates of these pass transistors to control lines controlling the transistors is tested by transmitting alternating high/low signals through serial conduction paths including the gate electrodes of these transistors.

Abstract: The integrity of a circuit processing logic signals is verified by use of switching means, including pass transistors, which are selectively varied to provide different test circuit configurations for different modes of operation. The circuit operates in normal, scan, test and data receive modes. During normal operation, the logic signal from the primary circuit is passed directly through a logic test block without the shifting of data in the logic test block.

Abstract: A power supply voltage level sensing circuit on an integrated circuit generates a reset signal that holds the components of the integrated circuit in a defined state when the power supply voltage level drops below a predetermined voltage. The reset signal is released when the power supply voltage level returns to above the predetermined voltage.The voltage level sensing circuit is comprised of two inverters and a filter circuit. The inverters start to conduct at different power supply voltage levels and have different trigger point characteristics.The power supply voltage level sensing circuit may be coupled with a power-on reset circuit to create a voltage sensing power-on reset circuit which generates a reset signal not only when the power supply voltage is first supplied to the circuit, but also when the power supply voltage level temporarily falls below a selected value.

Abstract: A configurable logic array comprises a plurality of configurable logic elements variably interconnected in response to control signals to perform a selected logic function. Each configurable logic element in the array is in itself capable of performing any one of a plurality of logic functions depending upon the control information placed in the configurable logic element. Each configurable logic element can have its function varied even after it is installed in a system by changing the control information placed in that element. Structure is provided for storing control information and providing access to the stored control information to allow each configurable logic element to be properly configured prior to the initiation of operation of the system of which the array is a part. Novel interconnection structures are provided to facilitate the configuring of each logic element.

Abstract: A programmable interconnect for programmably connecting transmission lines which are part of a configurable logic array is combined with a buffer at locations within the logic array where a signal will travel from a low capacitance line to a higher capacitance line. Use of a buffer in this arrangement allows for programmable interconnects controlling the configuration of the logic array to be smaller; consuming less power and providing for faster rise and fall of an output signal even when propagating through a long series of programmable interconnects. Several arrangements for programmably controlling the interconnect are taught. Also taught is a means of achieving a very wide AND gate without the need for cascading smaller devices.

Abstract: The integrity of a circuit processing logic signals is verified by use of switching means, including pass transistors, which are selectively varied to provide different test circuit configurations for different modes of operation. The circuit operates in normal, scan, test and data receive modes. During normal operation, the logic signal from the primary circuit is passed directly through a logic test block without the shifting of data in the logic test block.

Abstract: An emulator probe assembly for testing circuit boards which control programmable logic devices includes a header assembly, a universal pod, and an extender. The header assembly includes a socket, a plug, and a flexible cable. The header socket is matched in size to the socket of the circuit board so that during testing the programmable logic device can be inserted into the header socket and the header plug into the circuit board. Some pins in the header plug are connected directly to crresponding pins in the header socket. However other pins in the header plug are connected through lines in the flexible cable to contacts in a pod plug at the opposite end of the flexible cable. Corresponding pins in the header socket are also connected through the flexible cable to contacts in the pod plug. The pod plug is received by the universal pod which has electronics for controlling or receiving signals from the programmable logic device or the circuit board.

Abstract: A bidirectional buffer having a high impedance state is provided. This buffer is used for amplifying a signal as it is passed from one transmission line to another when it is desirable to select which direction the signal will flow. A switching circuit controls which transmission line is connected to the input terminal of the buffer and which is connected to the output terminal. A high impedance state is also provided for disconnecting the two transmission lines. Two memory cells control the direction of signal flow and the high impedance state.

Abstract: A TTL/CMOS compatible input buffer circuit comprises a Schmitt trigger input buffer stage and a reference voltage generator. In the TTL mode, the reference voltage generator supplies a reference voltage having a level that forces the trigger point of the Schmitt trigger to a predetermined value. In the CMOS mode, the reference voltage generator is disabled and a voltage equal to the power supply voltage is provided to the Schmitt trigger. The input buffer circuit affords an enhanced input noise margin and minimizes DC power loss.

Abstract: A microprocessor controlled configurable logic circuit achieves versatility by including a configurable combinational logic element, a configurable storage circuit, a configurable status buffer, and a configurable output select logic. The input signals to the configurable combinational logic element are input signals to the configurable logic circuit and feedback signals from the storage circuit. The storage circuit may be configured to operate as a D flip-flop with or without set and reset inputs, or as an edge detector. In conjunction with the combinational logic element, the storage circuit may also operate as a stage of a shift register or counter. The output select logic selects output from among the output signals of the combinational logic element and the storage circuit. The configurable status buffer may be configured to provide status information on selected important internal signals of the configurable logic circuit.

Abstract: A CMOS power-on reset circuit furnishes a reset signal for bringing the components of a circuit to a defined initial state when the common supply voltage is turned on. The output signal of the reset circuit assumes a first constant value as soon as the supply voltage rises above the level required to turn on the pulldown transistor of an initializing inverter in the reset circuit. A delay circuit causes the output signal of the reset circuit to remain at the first constant value for a period of time sufficient to allow the components of the circuit to settle. The output signal of the reset circuit is then forced to a second constant value. The reset circuit is suitable for use with power supply voltages which rise very rapidly or with power supply voltages which rise very slowly (DC sweep).

Abstract: Bidirectional amplifier employs a single buffer amplifier (64). The bidirectional amplifier is programmed by applying a control signal (Q) and its complementary signal (Q), which establishes the state of four pass transistors (P.sub.1 ', P.sub.2 ', P.sub.3 ', P.sub.4 ') or four CMOS transmission gates (T.sub.1, T.sub.2, T.sub.3, T.sub.4). For a first selection of the control signal, the bidirectional amplifier receives an input signal on a first lead (A') and produces an amplified signal on a second lead (B'). For a second selection of the control signal, the amplifier receives an input signal on the second lead (B') and produces an amplified output signal on the first lead (A').

Abstract: A configurable logic circuit achieves versatility by including a configurable combinational logic element, a configurable storage circuit, and a configurable output select logic. The input signals to the configurable combinational logic element are input signals to the configurable logic circuit and feedback signals from the storage circuit. The storage circuit may be configured to operate as a D flip flop with or without set and reset inputs, an RS latch, a transparent latch with or without set and reset inputs, or as an edge detector. In conjunction with the combinational logic element, the storage circuit may also operate as a stage of a shift register or counter. The output select logic selects output signals from among the output signals of the combinational logic element and the storage circuit.

Abstract: Bidirectional amplifier employs a single buffer amplifier (64). The bidirectional amplifier is programmed by applying a control signal (Q) and its complementary signal (Q), which establishes the state of four pass transistors (P'.sub.1, P'.sub.2, P'.sub.3, P'.sub.4) or four CMOS transmission gates (T.sub.1, T.sub.2, T.sub.3, T.sub.4). For a first selection of the control signal, the bidirectional amplifier receives an input signal on a first lead (A') and produces an amplified signal on a second lead (B'). For a second selection of the control signal, the amplifier receives an input signal on the second lead (B') and produces an amplified output signal on the first lead (A').

Abstract: A configurable logic array comprises a plurality of configurable logic elements variably interconnected in response to control signals to perform a selected logic function. Each configurable logic element in the array is in itself capable of performing any one of a plurality of logic functions depending upon the control information placed in the configurable logic element. Each configurable logic element can have its function varied even after it is installed in a system by changing the control information placed in that element. Structure is provided for storing control information and providing access to the stored control information to allow each configurable logic element to be properly configured prior to the initiation of operation of the system of which the array is a part. Novel interconnection structures are provided to facilitate the configuring of each logic element.