Abstract: The logic cell of the current invention is useful in a field programmable logic device, particularly a device in which an interconnect structure is interconnected by antifuses, and logic cells are programmed using pass transistors. All input leads of the logic cell can be selectively inverted. The output signal from one logic cell can be cascaded as input to the adjacent cell for efficiently computing wide functions. An optional feedback path allows the cell to be optionally used for sequential functions without the delay caused by a feedback path through field programmed connections. Configuration units can serve the multiple purposes of selectively applying programming voltages to the interconnect structure, shifting in configuration information for configuring the interconnect structure, and capturing and shifting out states of the interconnect lines. A novel output buffer allows 3-state control from multiple sources.

Abstract: An integrated circuit one shot circuit provides relatively long duration (hundreds of nanoseconds up to a millisecond) output pulses without the need for excessively large transistors. The one shot circuit includes a pull up and a pull down device connected to the one shot circuit's input terminal, with a latch connected to a node between the pull up and pull down devices. The output terminal of the latch is connected to the input of a Schmitt trigger. One terminal of a grounded capacitor is connected between the latch output terminal and the Schmitt trigger input. The output terminal of the Schmitt trigger is connected through an inverter to one input terminal of a NAND gate, the other input terminal of which is connected to the one shot circuit's input terminal. A feedback line connects the output terminal of the NAND gate to the gate of a depletion mode transistor which is between the pull up and pull down devices.

Abstract: For antifuse programmable integrated circuit devices, in particular FPGA devices, the invention allows for alternative routing around antifuses which fail to program. The chip architecture includes wiring segments and antifuses which together allow for alternative routes around every antifuse in the event of failure of that antifuse. The method includes programming the device under control of a computer which can recalculate routes in the event of an antifuse which fails to program. Preferably the initial routing distributes unused wiring segments through the chip to be available for routing around a failed antifuse. When a failure occurs, the method includes determining an alternative route around every failed antifuse. The alternative route may be established directly after the antifuse has failed or after all initially selected antifuses have been programmed.

Abstract: A set of module generators produce optimized implementations of particular circuit logic arithmetic functions for Field Programmable Gate Arrays (FPGAs) or other digital circuits. The module generators allow a circuit designer to spend more time actually designing and less time determining device-specific implementation details. The module generators accept a high level block diagram schematic of the circuit and automatically perform the detailed circuit design, including propagation of data types (precision and type) through the circuit, and low level circuit design optimization using a library of arithmetic and logic functions. The module generators are particularly useful for designs using field programmable gate arrays because of their unique architectures and ability to implement complex functions.

Abstract: The present invention allows initializing operations such as loading configuration data and preloading registers to begin before a user has released a reset signal. A circuit is provided which responds to the leading edge of a user's reset signal to generate an internal reset signal which begins the initializing operation. The circuit simultaneously starts a delayed signal which ends the internal reset signal. If the MRX signal is long, the chip becomes ready for operating upon release of the MRX signal, whereas if the MRX signal is short, the chip becomes ready for operating upon completion of any steps necessary for resetting the chip. In either case, after a reset signal is received, the chip becomes ready for operation in a shorter time than with the prior art circuits.

Abstract: A configurable cellular array is provided having a 2-dimensional array of cells in which each cell in the array has at least one input and output connection at least one bit wide to its neighbours. Each cell also has a programmable routing circuit to permit intercellular connections to be made. In one arrangement each cell contains a programmable function unit which includes a plurality of multiplexers. In a preferred arrangement the function unit and routing unit are programmable using associated Random Access Memory (RAM) areas within the cell. Each cell may be coupled to at least one global or array-crossing-signals so that all cells can be signalled simultaneously. The 2-dimensional array is rectangular and the intercell connections are orthogonal and are one bit wide.

Abstract: Power or ground voltage can fluctuate when many high capacitance terminals of an integrated circuit device move simultaneously from one logic state to another. This occurs particularly after release of a global high impedance state of output buffers where output signals have been passively driven to a selected logic state. To prevent supply and ground voltage variations, the buffers are provided with means for operating in a slow response (high skew) mode. A slew rate control circuit moves the buffer to slow response mode in response to the high impedance signal. When the slew rate control circuit receives a signal ending the high impedance state of the buffer, it applies a delay to this signal, and after the delay time allows the buffer to move to a fast response mode. The slow buffer response and resulting slow voltage change when high capacitance terminals move to a new logic state prevents fluctuation of power or ground voltage in response to simultaneous switching of many terminals.

Abstract: An improved Schmitt trigger, especially useful for large scale integrated circuit applications, includes a buffer (inverter) having a pull up device and two pull down devices all connected between a voltage supply and ground, and each receiving the input signal at its gate terminal. A node between the output terminals of the pull down devices is connected to the output terminal of the Schmitt trigger. A feedback line connects the output terminal of the Schmitt trigger to the gate of an N-channel depletion device connected between the pull-up and pull-down devices. Also provided are two devices to control the timing of the Schmitt trigger; these two control devices are connected between the output terminal of the Schmitt trigger and the output terminal of the inverter.Also provided in one embodiment is electrostatic discharge protection connected to the Schmitt trigger input and output terminals, and in another embodiment a control device for turning on and off the supply voltage to the inverter.

Abstract: This invention provides additional circuitry for a configurable logic array having logic functions which are programmed by loading memory cells which cause the logic array to generate a desired function. With the additional circuitry, the memory cells can also be used as memory for access by other parts of the logic array during operation.

Abstract: A programmable interconnect is provided that includes a first plurality of lines, a second plurality of lines, and means for connecting one of the first plurality of lines to one of the second plurality of lines, wherein the means for connecting includes an antifuse and a diode. The diode in this configuration performs the equivalent logical function as an AND gate. Programing the antifuse determines the diode-AND gate function performed. In this manner, a programmable interconnect array in accordance with the present invention, formed using standard fabrication processes, provides an area-efficient implementation of a wide AND functionality.

Abstract: An antifuse for programmable integrated circuit devices is formed above a refractory metal on a thin native oxide layer and comprises an amorphous compound resulting from an PECVD deposition using a combination of silane gas and nitrogen. After formation of the amorphous antifuse layer, the layer is implanted with an atomic species such as argon. The thin oxide layer is formed on the surface of a refractory metal, therefore the process of forming the oxide is slow, the oxide is of even thickness, and the thickness can be controlled precisely. In a preferred embodiment, a second thin oxide layer is formed above the doped amorphous layer. The oxide layers significantly reduce the leakage current of an unprogrammed antifuse. Because of these thin oxide layers and the implantation step, the amorphous layer may be as thin as 200 .ANG..

Abstract: A carry-lookahead structure for programmable architectures includes a number of M-bit carry lookahead units, each M-bit unit having two parallel programmable carry paths having AND gates controlled by configuration bits to program the beginning and end of an operating carry chain within the M-bit units, as well as the beginning locations in each unit, one path generating a first set of carry bits for the case of the carry-in equal to 0, and the other generating a second set of carry bits for the case of the carry-in equal to 1, and at least one multiplexer controlled by the carry-in for selecting one of the two carries at the most significant bit of the first and second sets of carry bits as carry-out of the unit. Each M-bit unit may further include multiplexers controlled by the carry-in for selecting which of the first and second sets of carry bits are the correct carry bits for addition and M sum logic elements for generating the outputs of sum bits.

Abstract: Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The circuit includes additional structures to allow the fast carry hardware to perform additional commonly used functions.

Abstract: An ESD protection circuit combines a split bipolar transistor with a transistor layout which exhibits very high tolerance to ESD events. The split bipolar transistor divides current among many segments and prevents the current hogging which often causes an ESD failure. Several splitting structures are disclosed, each combining a resistor in series with each segment to distribute current evenly. The transistor takes advantage of the snap-back effect to increase current carrying capacity. Layout positions metal contacts away from regions of highest energy dissipation. Layout also allows high currents to be dissipated through ESD protection structures and not through circuit devices such as output drivers or through parasitic bipolar transistors not designed for high current. Sharp changes in electron density are avoided by the use of high-diffusing phosphorus in N-regions implanted to both lightly and heavily doped levels. Critical corners are rounded rather than sharp.

Abstract: An antifuse is provided which includes a first conductive layer, an antifuse layer formed on the first conductive layer, and a second conductive layer formed on the antifuse layer. A portion of the antifuse layer forms a substantially orthogonal angle with the first conductive layer and the second conductive layer. This "corner" formation of the antifuse enhances the electric field at this location during programming, thereby providing a predictable location for the filament, i.e. the conductive path between the first and second conductive layers. This antifuse provides other advantages including: a relatively low programming voltage, good step coverage for the antifuse layer and the upper conductive layer, a low, stable resistance value, and minimal shearing effects on the filament.

Abstract: An field programmable gate array (FPGA) of cells arranged in rows and columns is interconnected by a hierarchical routing structure. Switches separate the cells into blocks and into blocks of blocks with routing lines interconnecting the switches to form the hierarchy. Also, select units for allowing memory bits to be addressed both individually and in large and arbitrary groups are disclosed. Further a control store for configuring the FPGA is addressed as an SRAM and can be dynamically reconfigured during operation.

Abstract: A method in accordance with the present invention includes programming a plurality of semiconductor devices simultaneously, thereby dramatically increasing the number of devices programmed within a predetermined time. In one embodiment, this method includes arranging a first plurality of semiconductor devices into an array configuration. The first array is then programmed while a second plurality of semiconductor devices is arranged into the array configuration. The second array is then programmed, while the first array is unloaded and a third plurality of semiconductor devices is arranged into the array configuration. The present invention further includes the step of moving the first plurality of semiconductor devices in the array configuration to a programming position and the step of transferring the first plurality of semiconductor devices to an unloading position.

Abstract: A circuit and method in a field programmable gate array (FPGA) for eliminating programming contentions which occur during array configuration comprises a switching matrix of crossing lines, in which cross points, called programmable interconnection points (PIPs), are connected by configuration transistors. The configuration transistors can be programmed to connect the lines at the PIPs or to leave the lines unconnected. Output drivers are selectively connected by the PIPs to the signal lines. Prior to the configuration and reconfiguration of the FPGA, drivers to the gate array are disabled to prevent potentially catastrophic driver contention. The contention eliminating circuit of the present invention holds the logical values of the output buffers to a single logic level until programming has been completed. The circuit of the preferred embodiment comprises a two input AND gate which combines the incoming data signals with a gating signal.

Abstract: A structure and method for configuring a field programmable gate array (FPGA). A configuration memory cell within the FPGA receives a programming signal. In response, the configuration memory cell provides a signal to a configuration control circuit to configure the FPGA. The configuration memory cell includes an input lead, a storage device and a selectable configuration circuit. The input lead carries the programming signal to the storage device. The storage device stores the programming signal and an inverted programming signal which is the inverse of the programming signal. The selectable configuration circuit can be selectably configured to provide the programming signal or the inverted programming signal to a first input lead of the configuration control circuit. The configuration control circuit couples (or decouples) various elements of the FPGA in response to the signal provided on the first input lead.

Abstract: A hybrid EPLD (chip) architecture has multiple first blocks each including a first type programmable AND array and multiple first type macrocells which are complex in structure and highly configurable; and multiple blocks each including a second type programmable AND array having fewer input lines and product term output lines than does the first type AND array, and multiple second type macrocells which have fewer logic gates than do the first type macrocells. The EPLD has a programmable interconnect matrix for interconnecting all the blocks.