Abstract: Highly integrated programmable arrays, in which a logic array integrated circuit chip is divided into configurable logic blocks interconnected by configurable interconnect lines, have been programmed by automatic means and methods. The present invention provides for allowing a user to manually specify the partitioning of a logic design, and to allow a user to retain portions of a previously partitioned, placed, and routed design when making revisions. To allow for manual control of partitioning, a library of symbols includes a partitioning symbol that specifies which primitive logic functions can be grouped. The user specifies which ports of primitive logic functions will correspond with ports on the logic block symbol. The present invention also allows for partitioning parts of a design before combining the parts.

Abstract: A CMOS or NMOS output buffer equalizes the number of logic gates in the signal paths connected to both the pull up and pull down transistors. In one embodiment, the pull down transistor signal path includes the conventional inverter connected to the output of a NAND gate. The pull up transistor signal path includes a CMOS passgate including two transistors connected together controlled by the output enable signal and passing the output data signal to a conventional output inverter stage. Also an additional transistor controlled by the output enable signal provides an additional signal to the input of the pull up transistor output inverter stage when the output enable signal is low. The provision of balanced signal paths in terms of number of gates and therefore propagation time to both the pull up and pull down transistors evens out the rise and fall crowbar switching current and thus minimizes switching noise.

Abstract: This invention provides additional circuitry for a configurable logic array having logic functions which are programmed by loading memory cells which cause the logic array to generate a desired function. With the additional circuitry, the memory cells can also be used as memory for access by other parts of the logic array during operation.

Abstract: A device for configuring portions of an array of memory cells for a programmable logic device comprises a data register, a plurality of shift registers and a control unit. The data are loaded into and out of the data register in parallel. Each of the outputs of the data register is coupled to a serial input of a respective shift register so the data can be shifted into the shift registers at the same time. A clock signal is applied by the control unit to the shift registers for serially loading the plurality of shift registers in parallel. The clock signal and the load signal are preferably applied simultaneously until the plurality of shift registers store a column of data to be transferred to the memory cells. The plurality of shift registers each have a plurality of data outputs. Each of the data outputs is coupled to a different row of memory cells. The control unit then generates an address signal to transfer the column of data held in the plurality of shift registers into the memory cells.

Abstract: A programmable gate array comprises an array of configurable logic blocks. Each configurable logic block is controlled by one or more rows and columns of memory cells in a memory array. According to the invention, an older bitstream may be used without modification in a newer programmable gate array. A frame register includes a plurality of active memory locations called frame bits which correspond to columns of memory cells within the memory array and at least one spare frame bit which does not correspond to a column of memory cells within the memory array. A similar configuration of row pointer cells comprises a shift register for enabling row by row addressing of the memory array.

Abstract: A programmable logic device includes a configuration memory expanded to store two or more complete sets of configuration data. A switch on the output of the configuration memory controls the selection of the configuration data applied to the configurable logic block. Each configurable logic block has one data storage device per set of configuration data. The configurable logic blocks may be re-configured within a user's clock cycle.During a first period, the switch on the output of the configuration memory selects and passes configuration data from the first set of configuration data. The configurable routing matrix and configurable logic block are configured according to this first set of configuration data and store results in a first storage device. During a second period, the switch selects and passes the second set of configuration data.

Abstract: A computer aided design system for electronic digital circuitry allows the circuit designer to design a circuit using high level block components, The designer specifies data type and precision (bus width) parameters as desired for whichever circuit blocks and/or busses he desires, Then the system propagates the data types and precision throughout the design automatically to achieve circuit-wide consistency, The system can also be used to verify a circuit design for data type and bus width consistency, The system can also be used to determine the mode of operation for the circuit blocks in the circuit.

Abstract: A logic block for a field programmable logic device which is of the type using memory bits in a look-up table to provide any function of several inputs, and which uses additional memory bits to control aspects of the configuration, achieves a smaller size by replacing memory bits which control some configuration choices of the logic block with multiplexers which alternately select a default configuration or allow the look-up table memory bits to control the configuration. Thus the memory bits perform an alternate function of serving as a look-up table to generate a function, and controlling gates such as multiplexers, XOR gates or AND gates to generate a function.

Abstract: According to the present invention hardware is provided in a user configurable logic integrated circuit chip to allow a user to select multiple storage functions such as D, T, JK, to receive multiple input signals and generate a storage input signal using a function such as OR or MUX, along with parallel load and asynchronous load options. A relatively small hardware area can offer these functions, which are commonly used, and can leave general purpose logic for other more complex functions, thus increasing the amount of logic which a user may implement in a given silicon area.

Abstract: A CMOS buffer includes an input inverter, and a pull-up circuit coupled to the input inverter. The pull-up circuit provides an additional, temporary, signal pull-up on the output terminal of the input inverter during a high to low signal transition on its input terminal. The pull-up circuit includes a means for creating a signal delay. In one embodiment, the means for creating a signal delay includes a second and third inverter in series, the second inverter receiving an output signal from the input inverter. The pull-up circuit further includes two transistors for transferring a high signal to an output line of the input inverter. One transistor is controlled by a signal transferred by the means for creating a delay. The other transistor is controlled by an input signal to the input inverter. This pull-up circuit configuration ensures that the signal transition from low to high is substantially equal to the signal transition from high to low on the output line of the input inverter.

Abstract: A low power optional inverter uses P-channel and N-channel transistors in series as in a conventional CMOS inverter, but in one embodiment connects complementary signals to the sources of the P-channel and N-channel transistors such that when the complementary signals are switched the circuit switches between an inverting and a non-inverting buffer. In some embodiments P-channel and/or N-channel pass transistors are used in the non-inverting mode to avoid the threshold voltage drop associated with a CMOS non-inverting buffer. In another embodiment, in the noninverting mode, at least one bypass transistor is turned on and power is not supplied to the inverter. In yet another embodiment, in the inverting mode a CMOS inverter is powered with conventional voltages and in the noninverting mode the CMOS inverter is disabled and a bypass transistor connects input to output.

Abstract: The tristate inverter of the present invention includes an input line, an output line, a first transistor for transferring a high signal to the output line, and a second transistor for transferring a low signal to the output line. The tristate inverter further includes means for isolating the input line from the second transistor, thereby significantly improving the rise time of the signal on the output line.

Abstract: A power-on reset circuit is provided which holds an integrated circuit device in a reset mode until at least two conditions are satisfied: supply voltage Vcc must be above a specified value and sense amplifiers in the device must be able to operate properly. Delay circuits and Schmitt trigger circuits also improve the stability of the signal which releases the device from its reset mode.

Abstract: The logic cell of the current invention is useful in a field programmable logic device, particularly a device in which an interconnect structure is interconnected by antifuses, and logic cells are programmed using pass transistors. All input leads of the logic cell can be selectively inverted. The output signal from one logic cell can be cascaded as input to the adjacent cell for efficiently computing wide functions. An optional feedback path allows the cell to be optionally used for sequential functions without the delay caused by a feedback path through field programmed connections. Configuration units can serve the multiple purposes of selectively applying programming voltages to the interconnect structure, shifting in configuration information for configuring the interconnect structure, and capturing and shifting out states of the interconnect lines. A novel output buffer allows 3-state control from multiple sources.

Abstract: This invention provides a structure and method for interconnecting logic devices through line segments which can be joined by programming antifuses. One of several programming lines can be connected through an interconnect line segment to each terminal of each antifuse in the array. Interconnect line segments connected to opposite terminals of the same antifuse are connected to a different programming line in order to be able to apply different voltages to the two terminals of the antifuse. An addressing structure selectively connects interconnect line segments to their respective programming lines, and programming voltages applied to the programming lines cause a selected antifuse to be programmed. A novel addressing feature sequentially addresses two transistors for the line segments to be connected, and takes advantage of a capacitive pumped decoder to maintain the addressed transistors turned on while programming voltages are applied.

Abstract: The logic cell of the current invention is useful in a field programmable logic device, particularly a device in which an interconnect structure is interconnected by antifuses, and logic cells are programmed using pass transistors. All input leads of the logic cell can be selectively inverted. The output signal from one logic cell can be cascaded as input to the adjacent cell for efficiently computing wide functions. An optional feedback path allows the cell to be optionally used for sequential functions without the delay caused by a feedback path through field programmed connections. Configuration units can serve the multiple purposes of selectively applying programming voltages to the interconnect structure, shifting in configuration information for configuring the interconnect structure, and capturing and shifting out states of the interconnect lines. A novel output buffer allows 3-state control from multiple sources.

Abstract: A hybrid EPLD (chip) architecture has multiple first blocks each including a first type programmable AND array and multiple first type macrocells which are complex in structure and highly configurable; and multiple blocks each including a second type programmable AND array having fewer input lines and product term output lines than does the first type AND array, and multiple second type macrocells which have fewer logic gates than do the first type macrocells. The EPLD has a programmable interconnect matrix for interconnecting all the blocks.

Abstract: A method is provided which includes on-chip identification of individual die. The first wafer sort includes the steps of programming a plurality of dice on a wafer, programming predetermined memory memory cells on each good die to identify the wafer on which that die is located, and storing the location of each good die in a file created for each wafer. Then, the plurality of dice are subjected to predetermined conditions. In the second wafer sort, predetermined memory cells on one die are accessed to determine the associated file of that die. The associated file is then loaded. Finally, the good dice are tested. In another embodiment, the first wafer sort includes identifying the first good die on the wafer. After the next good die on the wafer is found, that die is programmed to indicate the location of the proceeding good die. This programming step is repeated until the last good die on the wafer is programmed. Once again, the wafer is subjected to adverse conditions.

Abstract: The bit line for reading data in or writing data out from a CMOS integrated circuit latch is precharged to the trip point voltage of the latch (as determined by the latch's transistor design) shortly before the occurrence of a read operation. The precharging circuitry uses the latch circuit itself to generate the trip point, hence ensuring that the precharging circuit operates properly with regards to the latch characteristics in spite of temperature, voltage and fabrication process variations. The precharging circuitry ensures that during the operation of reading data from the latch, the bit line voltage never causes the latch to completely switch states, since at most the bit line voltage asymptotically approaches the trip point voltage. The precharging circuit is relatively simple, including only two logic gates and three other transistors.

Abstract: A TTL/CMOS compatible input buffer circuit comprises a Schmitt trigger input buffer stage and a reference voltage generator. In the TTL mode, the reference voltage generator supplies a reference voltage having a level that forces the trigger point of the Schmitt trigger to a predetermined value. In the CMOS mode, the reference voltage generator is disabled and a voltage equal to the power supply voltage is provided to the Schmitt trigger. The input buffer circuit affords an enhanced input noise margin and minimizes DC power loss.