Abstract: Method and apparatus for producing mask-configured integrated circuits which are pin, logic, and timing compatible substitutes for user-configured logic arrays, without the need for logic or timing simulations of the mask-configured circuit design. Scan testing networks of test blocks and modified flip flops are included in the mask-configured substitutes to test functionality. Logic compatibility to the user-configured logic array (an FPGA) is preserved by clustering together in the mask-configured integrated circuit (a gate array) all of the logic gates which perform the functions of a particular FPGA logic block. Moreover, only those FPGA logic gates or functions which are used are replicated in the gate array, to conserve chip area. Test blocks are inserted in the gate array only where needed, i.e. at the output of any function generator that has connections external to the configurable logic block, and all flip flops are modified to also function as test blocks in a test mode.

Abstract: Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The circuit includes additional structures to allow the fast carry hardware to perform additional commonly used functions. In some embodiments, the circuit also includes structures which allow efficient implementation of a loadable counter and related applications.

Abstract: A reconfigurable sense amplifier in accordance with the present invention operates in either a high switching speed mode, where power consumption is a less critical consideration, or in a low power consumption mode, where switching speed is a less critical consideration. In a high speed mode, the present invention provides an additional pull-up to an amplified bitline which in combination with an existing weak pull-up still permits the signal on the amplified bitline to be affected by a change in voltage on the bitline. In a low power mode, the present invention provides a temporary pull-up on the amplified bitline if a signal on a wordline is transitioning from high to low (i.e. indicating that a low-to-high signal transition may occur on the bitline). In this manner, the present invention anticipates that when such a transition occurs, the voltage on the amplified bitline may also increase.

Abstract: An erasable programmable logic device (EPLD) includes function blocks connected by a universal interconnect matrix (UIM). The UIM includes both a cross-point circuit and a multiplexer-based (MUX-based) circuit. The cross-point circuit includes intersecting first and second conductors programmably connected by memory cells having control gates connected to the first conductors, drains connected to the second conductors, and sources connected to ground. The MUX-based circuit includes third and fourth conductors programmably connected by pass-gates having first terminals connected to the third conductors, second terminals connected to the fourth conductors, and gates connected to memory cells. The UIM further includes multiple-input multiplexers having first input lines connected to the cross-point circuit, second input lines connected to the MUX-based circuit, and output lines connected to the input lines of the function blocks.

Abstract: An field programmable gate array (FPGA) of cells arranged in rows and columns is interconnected by a hierarchical routing structure. Switches separate the cells into blocks and into blocks of blocks with routing lines interconnecting the switches to form the hierarchy. Also, select units for allowing memory bits to be addressed both individually and in large and arbitrary groups are disclosed. Further a control store for configuring the FPGA is addressed as an SRAM and can be dynamically reconfigured during operation.

Abstract: A method and structure for a configurable flip flop circuit. The configurable flip flop circuit includes a flip flop, a first signal line for receiving a first signal, a second signal line for receiving a second signal, a first enable line for receiving a first enable signal, a second enable line for receiving a second enable signal, a programmable logic circuit and a multiplexer circuit. The programmable logic circuit receives the first and second enable signals from the first and second enable lines. In response, the programmable logic circuit generates multiplexer control signals which are provided to the multiplexer circuit. The multiplexer circuit selectably couples the first signal line, the second signal line, and the output terminal of the flip flop to the flip flop input terminal in response to the multiplexer control signals.

Abstract: An AND array for an erasable programmable logic device (EPLD) includes word-line transition detectors for indicating high-to-low word-line transitions. Such transitions are a condition precedent for low to-high bit line transitions. Transition indications are buffered by a fast transition-detection sense amplifier, the output of which is provided to each of plural "mode-switchable" sense amplifiers that read out the bit lines for the AND array. Each mode-switchable sense amplifier logically combines the transition indication with its own output to select its operating mode. A fast (strong source-current) mode is entered only when,the transition indication is active and the present output of the sense amplifier is low. Otherwise, which is most of the time, the mode switchable sense amplifier remains in a low-power (weak source-current) mode. This arrangement provides higher speed operation with relatively low time-averaged power consumption.

Abstract: Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The invention takes advantage of the fact that a carry signal to be added to two bits can be propagated to the next more significant bit when the two binary bits to be added are unequal, and that one of the bits can serve as the carry signal when the bits are equal.

Abstract: The present invention provides a memory cell which includes a pair of flash EEPROM cells. One flash EEPROM cell is programmed and the other flash EEPROM cell is simultaneously erased by a single programming pulse. Because the configuration memory cell includes flash EEPROM cells, and therefore is non-volatile, a power down does not require reprogramming or refreshing of the configuration bit stored in the memory cell.

Abstract: A sense amplifier of the present invention provides power savings of between 30% to 70% for typical usage of a programmable logic device. In one embodiment, this sense amplifier includes circuitry for detecting and propagating the logic state on a bit line, an amplifier for amplifying the propagated logic state, and configuration logic for receiving a first configuration bit and a second configuration bit. If the first configuration bit and the second configuration bit have different logic states (indicating a non-toggling state), then the sense amplifier mimics the bit line at either a first logic state or a second logic state. Specifically, if the first configuration bit has the first logic state and the second configuration bit has the second logic state, then the sense amplifier mimics the bit line at the first logic state.

Abstract: A method for programming a programmable logic device (FPLD) to implement a circuit design using a library of elements made up of general logic functions and an invert function. The general logic functions represent groups of the 2.sup.2.spsp.n specific logic functions which can be stored in an n-input lookup table addressing 2.sup.n data signals. The specific logic functions of each group differ by one or more inverted input signals and/or an inverted output signal. The method includes the step of technology mapping the circuit design using the library of elements. The general logic functions are assigned a finite value and the invert function is assigned a zero cost (or a very small cost). A subcircuit of the circuit design having n input signals (or less) and one output will always match one logic element from this library.

Abstract: The present invention provides suggested delay limits for use by layout tools which cause a programmable integrated circuit device to implement a logic design. The suggested delay limits can be used by such tools as an initial placement algorithm, a placement improvement algorithm, and a routing algorithm for evaluating and guiding potential layouts. The suggested delay limits take into account characteristics of the programmable device being used by estimating lower bound delays for each connection in a logic design, and take into account any previously achieved delays or achievable delays for each connection in calculating the suggested limits. Results of routing benchmark designs using the novel suggested limits show improved timing performance for all benchmark cases tested.

Abstract: A bidirectional tristate buffer includes a default input such that the signal applied to one of the lines connected to the bidirectional buffer is always applied to the input terminal of a buffer element in the bidirectional buffer and applied by the output terminal of the buffer element to any load which may be driven by the buffer output terminal. In a preferred embodiment, the tristate bidirectional buffer with default input requires only four transistors plus the transistors which comprise the buffer element and memory cells for controlling the direction.

Abstract: A modified partitioning method for placement of a circuit design into a programmable integrated circuit device having a specific distribution of physical resources along a horizontal or vertical line in the device. The circuit design includes a plurality of circuit elements, for example three-state buffers which feed a common bus, or registers which receive a common clock signal. Such elements should or must be placed along a single horizontal or vertical line. One method includes the step of weighting connecting lines (nets) which join circuit elements to be placed along a common line with different weights for the horizontal and vertical directions. Alternatively, elements to be placed along the line are marked to be kept in line during partitioning. A min-cut algorithm then tends to or is required to avoid separating particular elements from a common line.

Abstract: The present invention provides a sense circuit including a first bit line, a second bit line, a first plurality of memory cells coupled to the first bit line, a second plurality of memory cells coupled to the second bit line, and selection circuitry coupled to the first bit line and the second bit line. The selection circuitry provides a wide AND gate function in one mode and provides a zero power circuit for generating a function of a single input in another mode.

Abstract: The present invention provides a programmable logic circuit including a first set of lines coupled to a logic module, a second set of lines, and a plurality of transistors. Each transistor in the array has a first terminal, a second terminal, and a third terminal, wherein the first terminal is coupled to one of the first set of lines and the second terminal is coupled to one of the second set of lines. In accordance with the present invention, an antifuse is coupled between the third terminal of the transistor and a voltage source. By selectively programming antifuses in the array and selectively turning on transistors, complex user functions with a large number of inputs are implemented in one pass.

Abstract: An input clock delay circuit includes an up counter for estimating the approximate number of internal clock cycles that occur during one cycle of the input clock signal and another up counter for determining the portion of each cycle of the input clock signal that is high. A clock manipulation circuit receives each counter's value, and may be set to perform a fixed transform on the input clock signal, such as clock delay/advance, duty cycle shifting, and frequency multiplication/division. The clock manipulation circuit output values are loaded into two down counters that are also clocked by the internal clock. On the rising edge of the input clock signal, the first down counter starts decrementing until the counter reaches zero, indicating that the desired delay interval has passed, at which point the delayed output clock signal is taken high. The second down counter then starts decrementing for an interval that is equal to the desired duty cycle of the output clock signal.

Abstract: In a programmable integrated circuit device, a pad interface structure is provided in which the number of pads connected to the interface structure is selectively changed without redesigning the interface structure or redesigning the chip interior.

Abstract: An antifuse is provided which includes a first conductive layer, an antifuse layer formed on the first conductive layer, and a second conductive layer formed on the antifuse layer. A portion of the antifuse layer forms a substantially orthogonal angle with the first conductive layer and the second conductive layer. This "corner" formation of the antifuse enhances the electric field at this location during programming, thereby providing a predictable location for the filament, i.e. the conductive path between the first and second conductive layers. This antifuse provides other advantages including: a relatively low programming voltage, good step coverage for the antifuse layer and the upper conductive layer, a low, stable resistance value, and minimal shearing effects on the filament.

Abstract: An field programmable gate array (FPGA) of cells arranged in rows and columns is interconnected by a hierarchical routing structure. Switches separate the cells into blocks and into blocks of blocks with routing lines interconnecting the switches to form the hierarchy. Also, select units for allowing memory bits to be addressed both individually and in large and arbitrary groups are disclosed. Further a control store for configuring the FPGA is addressed as an SRAM and can be dynamically reconfigured during operation.