Patents Assigned to Xilinx, Inc.
  • CMOS analog circuits having a triode-based active load
    Patent number: 10998307
    Abstract: An analog signal buffer is disclosed. The analog signal buffer may include a transconductance cell and an active load. The active load may load the current from the transconductance cell with a PMOS transistor and an NMOS transistor and provide a feedback resistance. A transimpedance amplifier is disclosed. The transimpedance amplifier may include a first cell configured to receive a first signal and output a second signal and a second cell coupled to the first cell. The second cell may include an active feedback structure configured to couple an output of the second cell to an input of the second cell.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: May 4, 2021
    Assignee: Xilinx, Inc.
    Inventors: Kevin Zheng, Chuen-Huei Chou, Hsung Jai Im
  • SUBSYSTEM FOR CONFIGURATION, SECURITY, AND MANAGEMENT OF AN ADAPTIVE SYSTEM
    Publication number: 20210124711
    Abstract: An integrated circuit (IC) can include a processor system configured to execute program code, a programmable logic, and a platform management controller coupled to the processor system and the programmable logic. The platform management controller is adapted to configure and control the processor system and the programmable logic independently.
    Type: Application
    Filed: October 28, 2019
    Publication date: April 29, 2021
    Applicant: Xilinx, Inc.
    Inventors: Ahmad R. Ansari, Sagheer Ahmad
  • Dynamically reconfigurable networking using a programmable integrated circuit
    Patent number: 10990547
    Abstract: A device includes a platform implemented, at least in part, in a static region of programmable circuitry and a dynamic region of programmable circuitry configured to implement user-specified circuitry in communication with the platform. The platform is configured to establish and maintain a first communication link with a host data processing system and a second communication link with a network while at least a portion of the dynamic region of programmable circuitry is dynamically reconfigured.
    Type: Grant
    Filed: August 11, 2019
    Date of Patent: April 27, 2021
    Assignee: Xilinx, Inc.
    Inventors: Chandrasekhar S. Thyamagondlu, Ravi Sunkavalli, Ravi N. Kurlagunda, Ellery Cochell
  • Streaming interconnect architecture for data processing engine array
    Patent number: 10990552
    Abstract: Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include a memory module (with memory banks for storing data) and an interconnect which provides connectivity between the engines. To transmit processed data, a data processing engine identifies a destination processing engine in the array. Once identified, the data processing engine can transmit the processed data using a reserved point-to-point communication path in the interconnect that couples the source and destination data processing engines.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: April 27, 2021
    Assignee: XILINX, INC.
    Inventors: Goran Hk Bilski, Peter McColgan, Juan J. Noguera Serra, Baris Ozgul, Jan Langer, Richard L. Walke, Ralph D. Wittig, Kornelis A. Vissers, Philip B. James-Roxby, Christopher H. Dick
  • Auto-precharge management in a controller
    Patent number: 10991417
    Abstract: A system includes a queue and a controller. The queue receives a transactions from masters to access a memory component. The memory component includes a plurality of rows. The controller issues a command to access a row of the plurality of rows in response to receiving a first issued transaction. The first issued transaction is issued by a first master. The controller is configured to prevent issuing an auto-precharge command to keep the row associated with the first issued transaction open if a subsequent transaction in the queue from the first master accesses a same row as the first transaction. The controller is configured to prevent issuing the auto-precharge command to keep the row associated with the first issued transaction open if the controller receives data associated with keeping the row associated with the first issued transaction open.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: April 27, 2021
    Assignee: XILINX, INC.
    Inventor: Ygal Arbel
  • Configurable overlay on wide memory channels for efficient memory access
    Patent number: 10990517
    Abstract: Examples described herein relate to efficient memory access. An example is a system includes a programmable device, and a memory. The programmable device is coupled to the host and receives the read/write requests and the addresses associated therewith. The programmable device interleaves the read/write requests across multiple communication channels based on a subset of bits within each address. The memory receives the read/write requests from the programmable device. The memory stores contents associated with the addresses for write requests and returns contents associated with the addresses for a read request to the programmable device. The programmable device returns the received contents to the host for processing.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: April 27, 2021
    Assignee: XILINX, INC.
    Inventors: Hare K. Verma, Jiayou Wang, Vincent Mirian
  • Programmable pipeline at interface of hardened blocks
    Patent number: 10990555
    Abstract: Embodiments herein describe an interface between PL fabric and a hardened block that includes a programmable pipeline. This pipeline includes at least a sequential element and a bypass path. For time critical nets in a netlist, the programmable IC routes a net through the sequential element. Doing so mitigates or eliminates the uncertainty associated with routing the net from the hardened block through PL fabric. Also, the sequential element can increase the available time for capturing the data. For less time critical nets, the net can route through the bypass path. This means the route from the hardened block to the PL fabric is determined on the fly by a routing algorithm rather than being fixed.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: April 27, 2021
    Assignee: XILINX, INC.
    Inventors: Aashish Tripathi, Sundeep Ram Gopal Agarwal
  • Implementing a circuit design with re-convergence
    Patent number: 10990736
    Abstract: Implementing a circuit design can include detecting, using computer hardware, a re-convergent section of a circuit design, masking, using the computer hardware, a sequential circuit element of the re-convergent section located between a start and an end of the re-convergent section, and performing, using the computer hardware, an optimization operation on combinatorial logic of the re-convergent section to create optimized combinatorial logic. Using the computer hardware, the optimized combinatorial logic of the re-convergent section can be mapped. Further, the re-convergent section can be modified subsequent to the mapping to match timing of the re-convergent section prior to the masking.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: April 27, 2021
    Assignee: Xilinx, Inc.
    Inventors: Chaithanya Dudha, Satyaprakash Pareek, Krishna Garlapati, Ashish Sirasao
  • Object detection in video
    Patent number: 10990826
    Abstract: Detecting objects in video may include receiving object detections for a plurality of selected frames of a video from a still image detector, wherein the plurality of selected frames are non-adjacent frames of the video, propagating the object detections from the plurality of selected frames to sequential frames of the video adjacent to the plurality of selected frames based on a distance metric and vector flow data for the sequential frames, suppressing false positive object detections from the propagating, and outputting resulting object detections for the sequential frames of the video.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: April 27, 2021
    Assignee: Xilinx, Inc.
    Inventors: Mujib Haider, Venkata V. Dhanikonda, Ashish Sirasao
  • Phase detector offset to resolve CDR false lock
    Patent number: 10985764
    Abstract: An example method of clock and data recovery (CDR) includes adding a pre-defined offset to an output of a phase detector (PD) of a CDR circuit, and loading an accumulator of a frequency loop of the CDR circuit with a pre-defined load value. The method further includes detecting the phase of an incoming signal using a PD, and determining that the CDR has locked onto a real lock point. In some examples, the method further includes determining that the CDR has locked on a real lock point, and, in response to the determination, modifying the pre-defined offset to equal zero.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: April 20, 2021
    Assignee: XILINX, INC.
    Inventors: Winson Lin, Jin Namkoong, Hongtao Zhang
  • Customizable multi queue DMA interface
    Patent number: 10983920
    Abstract: Examples herein describe techniques for providing a customizable direct memory access (DMA) interface which can permit user logic to change or control how DMA read and writes are performed. In one example, a DMA engine may be hardened (e.g., include circuitry formed from a semiconductor material) which prevents the DMA engine from being reconfigured like programmable logic. Instead of changing the DMA engine, the user logic can change or customize the DMA interface between the user logic and the DMA engine. In this way, the manner in which the DMA engine performs DMA write and reads can be changed by the user logic. In one example, the DMA engine includes a bypass mode of operation where descriptors associated with DMA queues are passed through the DMA engine and to the user logic.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: April 20, 2021
    Assignee: XILINX, INC.
    Inventors: Chandrasekhar S Thyamagondlu, Darren Jue, Tao Yu, John West, Hanh Hoang, Ravi Sunkavalli
  • Inline image preprocessing for convolution operations using a matrix multiplier on an integrated circuit
    Patent number: 10984500
    Abstract: An example preprocessor circuit for formatting image data into a plurality of streams of image samples includes: a plurality of memory banks configured to store the image data; multiplexer circuitry coupled to the memory banks; a first plurality of registers coupled to the multiplexer circuitry; a second plurality of registers coupled to the first plurality of registers, outputs of the second plurality of registers configured to provide the plurality of streams of image samples; bank address and control circuitry coupled to control inputs of the plurality of memory banks, the multiplexer circuitry, and the first plurality of registers; output control circuitry coupled to control inputs of the second plurality of registers; and a control state machine coupled to the bank address and control circuitry and the output control circuitry.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: April 20, 2021
    Assignee: XILINX, INC.
    Inventors: Ashish Sirasao, Elliott Delaye, Aaron Ng, Ehsan Ghasemi
  • Method and apparatus for multi-voltage domain sequential elements
    Patent number: 10979034
    Abstract: A circuit includes a master latch circuit and a slave latch circuit. The master latch circuit is configured to receive an input data signal associated with an input data voltage domain and generate a first output data signal associated with an output data voltage domain different from the input data voltage domain. The slave latch circuit is configured to receive, from the master latch circuit, the first output data signal and generate a second output data associated with the output data voltage domain.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: April 13, 2021
    Assignee: XILINX, INC.
    Inventors: Kumar Rahul, Santosh Yachareni, Jitendra Kumar Yadav, Md Nadeem Iqbal, Teja Masina, Sourabh Swarnkar, Suresh Babu Kotha
  • Dynamic scan chain and method
    Patent number: 10977404
    Abstract: Disclosed approaches for dynamically creating one or more scan chains in a programmable integrated circuit (IC) include placing elements of a circuit design on first registers of the programmable IC. A processor can determine second registers of the programmable IC that are unused by the circuit design after placing the elements of the circuit design. Data-out pins of the first registers are coupled to data-in pins of the second registers, respectively, and the second registers are coupled into a scan chain.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: April 13, 2021
    Assignee: XILINX, INC.
    Inventors: Srinivas T. Reddy, Dinesh Gaitonde, Ritesh Mani
  • Preparation of circuit designs for system-on-chip devices and implementation of circuitry using instances of a logical network-on-chip
    Patent number: 10977401
    Abstract: Disclosed approaches for creating a circuit design involving a network-on-chip (NoC) include instantiating in a memory of a computer system logic blocks and logical NoC (LNoC) blocks. Each logic block specifies a function of the circuit design and is communicatively coupled to another logic block through an LNoC block. The LNoC blocks are aggregated into a traffic specification that specifies connections between ingress circuits and egress circuits of the NoC. The traffic specification is compiled into configuration parameters for circuits of the NoC, and the logic blocks are compiled into implementation data for the target IC by the computer processor. The target IC can then be configured with the configuration parameters and implementation data.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: April 13, 2021
    Assignee: XILINX, INC.
    Inventors: Jeffrey M. Arnold, Stephen L. Bade, Srinivas Beeravolu, Chukwuweta Chukwudebe, Anindita Patra, Nabeel Shirazi
  • Efuse bank and associated anchor bits
    Patent number: 10978167
    Abstract: A disclosed circuit arrangement includes a bank of efuse cells, first and second sense amplifiers coupled to input signals representing constant logic-1 and logic-0 values, respectively, a storage circuit, an efuse control circuit, and an efuse security circuit. The efuse control circuit inputs signals from the bank of efuse cells and signals that are output from the first and second sense amplifiers, and stores data representative of values of the signals in the storage circuit. The efuse security reads the data from the storage circuit and generates an alert signal having a state that indicates a security violation in response to data representative of the value of the signal from the first sense amplifier indicating a logic-0 value or data representative of the value of the signal from the second sense amplifier indicating a logic-1 value.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: April 13, 2021
    Assignee: XILINX, INC.
    Inventors: James D. Wesselkamper, Edward S. Peterson, Jason J. Moore, Steven E. McNeil
  • Dynamic base address register (BAR) reconfiguration using a peripheral component interconnect express (PCIe) extended configuration space
    Patent number: 10977051
    Abstract: Some examples described herein provide for dynamically reconfiguring a base address register (BAR) of a Peripheral Component Interconnect Express (PCIe) configuration space. In an example, information relating to a BAR of a PCIe configuration space is written to a PCIe extended configuration space of the PCIe configuration space, which is read, by a dynamic BAR module. Respective values are written, by the dynamic BAR module, to bits of the BAR based on the information. After writing by the dynamic BAR module, a set value is attempted to be written to each of address bits of the BAR. Writing the set value to an address bit of the BAR is prevented when the address bit is set to a predefined value. After attempting to write, a read value is read from the bits of the BAR. A base address of memory is written to the BAR based on the read value.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: April 13, 2021
    Assignee: XILINX, INC.
    Inventors: Christopher Y. Karman, Vidya Gopalakrishnan, Ramesh Barukula
  • Development environment for heterogeneous devices
    Patent number: 10977018
    Abstract: Implementing an application within a heterogeneous device can include receiving an application specifying a plurality of hardware accelerators and having a plurality of sections corresponding to different subsystems of the heterogeneous device, wherein the plurality of sections are specified using different programming models. Compiling each section based on the programming model of the section and the subsystem of the heterogeneous device corresponding to the section into an accelerator representation. Linking the accelerator representations based on a platform of the heterogeneous device, generating a hardware implementation of the application for the heterogeneous device based on the linked accelerator implementations, and automatically generating program code configured to control one or more of the plurality of hardware accelerators of the hardware implementation.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: April 13, 2021
    Assignee: Xilinx, Inc.
    Inventors: L. James Hwang, Michael Gill, Tom Shui, Jorge E. Carrillo, Alfred Huang, Sudipto Chakraborty
  • Synchronization headers for serial data transmission with multi-level signaling
    Patent number: 10979210
    Abstract: Techniques for handling synchronization headers for serial data transmission with multi-level signaling are described. In an example, a transmitter includes a multiplexer circuit configured to serialize an input signal to generate an output bit sequence having a plurality of bits between pairs of synchronization header bits. The transmitter includes a re-ordering circuit, coupled to the multiplexer circuit to receive the output bit sequence, configured to re-order the output bit sequence by moving at least one of the plurality of bits between the synchronization header bits in each of the pairs of synchronization header bits. The transmitter includes an output driver circuit configured to drive the re-ordered output bit sequence onto a transmission medium.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: April 13, 2021
    Assignee: XILINX, INC.
    Inventor: Ben J. Jones
  • Latency synchronization across clock domains
    Patent number: 10969821
    Abstract: Methods and apparatus for tracking delay in signals sent from a first clock domain to a second clock domain are disclosed. For example, at a first time a common timing reference signal (SysRef) may be received at the first clock domain, and a latency marker may be input into a first-in first-out data structure (FIFO) coupling the first clock domain to the second clock domain. At a second time, the SysRef may be received at the second clock domain, and a timer may be started at the second clock domain. At a third time, the latency marker may be received from the FIFO at the second clock domain, and the counter may be stopped at a final count. A FIFO latency may be determined based on the final count and on a difference between the second time and the first time.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: April 6, 2021
    Assignee: XILINX, INC.
    Inventors: Ryan Kinnerk, Bob W. Verbruggen, John E. McGrath