Abstract: State machine generation for a multi-buffer electronic system can include receiving, using a processor, a user input specifying a reader policy and a number of a plurality of buffers used by a reader and a writer of the multi-buffer electronic system. A state machine can be generated as a data structure. The state machine has a plurality of states determined based on the number of the plurality of buffers and the reader policy. The state machine allocates different buffers of the plurality of buffers to the reader in temporally accurate order over time. Each state can specify an allocation from the plurality of buffers to the reader and the writer. A state machine description including one or more program code components can be generated, where the one or more program components may be used in an implementation of the reader and an implementation of the writer.

Abstract: Examples described herein generally relate to testing of bonded wafers and structures implemented for such testing. In an example method, power is applied to a first pad on a stack of bonded wafers. A wafer of the stack includes a process control monitor (PCM) region that includes structure regions. Each structure region is a device under test region, dummy region, and/or chain interconnect region (CIR). The stack includes a serpentine chain test structure (SCTS) electrically connected between first and second metal features in the wafer in first and second CIRs, respectively, in the PCM region. The SCTS includes segments, one or more of which are disposed between neighboring structure regions in the PCM region that are not the first and second CIRs. A signal is detected from a second pad on the stack. The first and second pads are electrically connected to the first and second metal features, respectively.

Abstract: A differential signal input buffer is disclosed. The differential signal input buffer may receive a differential signal that includes a first signal and a second signal and may be divided into a first section and a second section and. The first section may buffer and/or amplify the first signal based on a first level-shifted second signal. The second section may buffer and/or amplify the second signal based on a first level-shifted first signal. In some implementations, the first section may buffer and/or amplify the first signal based on a second level-shifted second signal. Further, in some implementations, the second section may buffer and/or amplify the second signal based on a second level-shifted first signal.

Abstract: A network interface device, said network interface device has a data transmission path configured to receive data for transmission. The data for transmission is to be sent over a network by the network interface device. A monitor is configured to monitor the data transmission path to determine if an underrun condition is associated with the data transmission path. If so, an indication is included in the transmitted data packet.

Abstract: Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include streaming interconnects which transmit streaming data using two different modes: circuit switching and packet switching. Circuit switching establishes reserved point-to-point communication paths between endpoints in the interconnect which routes data in a deterministic manner. Packet switching, in contrast, transmits streaming data that includes headers for routing data within the interconnect in a non-deterministic manner. In one embodiment, the streaming interconnects can have one or more ports configured to perform circuit switching and one or more ports configured to perform packet switching.

Abstract: Disclosed herein are integrated circuit devices and methods for fabricating the same that include at least one non-I/O die having ESD protection circuitry. The ESD protection circuitry disclosed herein may also be utilized in I/O dies. In one example, an integrated circuit device includes a die having a first body. First and second contact pads are exposed to a surface of the first body. The first contact pad is configured to connect to a first supply voltage. The second contact pad is configured to connect to a second supply voltage or ground. A first charge-sensitive circuitry formed in the first body is coupled between the first and second contact pads. A first RC clamp formed in the first body is coupled between the first and second contact pads. The first RC clamp includes at least two BigFETs coupled between the first and second contact pads, and a trigger circuitry coupled in parallel to gate terminals of the at least two BigFETs.

Abstract: Examples described herein provide techniques for multi-die device structures having improved gap uniformity between neighboring dies. In some examples, a first die and a second die are attached to an interposer. A first gap is defined by and between the first die and the second die. At least one of the first die or the second die is etched at the first gap. The etching defines a second gap defined by and between the first die and the second die. The first die, the second die, and the interposer are encapsulated with an encapsulant. The encapsulant is disposed in the second gap.

Abstract: Integrated circuit (IC) dies and method for manufacturing the same are described herein that mitigate pattern loading effects during manufacture. In one example, the IC includes a die body having a first circuit block separated from an adjacent second circuit block by a buffer zone. The first and second circuit blocks have first and second transistors that are at least partially fabricated from a gate metal layer and disposed immediately adjacent the buffer zone. A dummy structure is formed in the buffer zone and is also at least partially fabricated from the gate metal layer. An amount of gate metal layer material in the dummy structure is selected to mitigate differences in the amount of gate metal layer material in regions of first and second circuit blocks that neighbor each other across the buffer zone.

Abstract: The embodiments herein creates DCT mechanisms that initiate a DCT at the time the updated data is being evicted from the producer cache. These DCT mechanisms are applied when the producer is replacing the updated contents in its cache because the producer has either moved on to working on a different data set (e.g., a different task) or moved on to working on a different function, or when the producer-consumer task manager (e.g., a management unit) enforces software coherency by sending Cache Maintenance Operations (CMO). One advantage of the DCT mechanism is that because the direct cache transfer takes place at the time the updated data is being evicted, by the time the consumer begins its task, the updated contents have already been placed in its own cache or another cache within the cache hierarchy.

Abstract: Examples herein describe techniques for generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges (e.g., the communication links between the kernels). A compiler converts the source code into a bitstream and/or binary code which configures programmable and non-programmable logic in a heterogeneous processing environment of a SoC to execute the graph. The compiler can also consider user-defined constraints when compiling the source code. The constraints can dictate where the kernels and buffers should be placed in the heterogeneous processing environment, performance requirements, data communication routes through the SoC, type of data path, delays, and the like.

Abstract: A circuit for signal classification in a digital pre-distortion (DPD) system is provided. The circuit includes a first frequency path with a positive frequency translation to generate a first power level corresponding to a signal output of the first frequency path, a second frequency path with a negative frequency translation to generate a second power level corresponding to a signal output of the second frequency path, and a third frequency path configured to filter the input signal via a high pass filter (HPF) and to generate a third power level corresponding to a signal output of the third frequency path. The circuit further includes a processing unit configured to compute frequency content metrics corresponding to the input signal based on the first power level, the second power level and the third power level for selecting a set of DPD coefficients for the DPD circuit.

Abstract: A quadrature clock generator is disclosed. The quadrature clock generator may include a first injection-locked oscillator, a phase interpolator, and a second injection-locked oscillator. The first injection-locked oscillator may generate a first plurality clock signals from a first reference clock signal. The phase interpolator may generate a second reference clock signal from the first plurality of clock signals, and the second injection-locked oscillator may generate a second plurality of clock signals from the second reference clock signal. A first quadrature clock signal may be selected from the first plurality of clock signals and a second quadrature clock signal may be selected from the second plurality of reference clock signals.

Abstract: A circuit arrangement includes a buffer, a height traversal circuit configured to generate a sequence of IFM height values in response to first control signals, a width traversal circuit configured to generate a sequence of IFM width values in response to second control signals, a control circuit, and an address generation circuit. The control circuit is configured to input an OFM height, an OFM width, a kernel height, and a kernel width; generate the first control signals at times based on the OFM height and the kernel height; and generate the second control signals at times based on the OFM width and the kernel width. The address generation circuit is configured to generate a sequence of addresses based on the sequences of IFM height values and IFM width values, provide the sequence of addresses to the buffer, and enable reading from the buffer.

Abstract: An improved chip package, and methods for fabricating the same are provided that utilize two tier packaging of an optical die and another die commonly disposed over a substrate. In one example, a chip package is provided that includes an optical die, a core die, and an electrical/optical interface die are all disposed over a common substrate. In one example, a first routing region is provided between the core and electrical/optical interface dies, a second routing region is provided between the electrical/optical interface die and the optical dies, and a third routing region is disposed between the substrate and the core and electrical/optical interface dies.

Abstract: Examples described herein provide for methods for semiconductor processing for forming source/drain regions of transistors. An example is a method for semiconductor processing. An etch stop liner is formed in a semiconductor substrate. Forming the etch stop liner includes implanting etch selectivity dopants into the semiconductor substrate. The etch selectivity dopants form at least part of the etch stop liner. A source/drain cavity is formed in the semiconductor substrate. Forming the source/drain cavity includes etching the etch stop liner. Etching the etch stop liner selectively etches the etch stop liner relative to a material of the semiconductor substrate. A source/drain region is epitaxially grown in the source/drain cavity.

Abstract: A decoder circuit includes a low-density parity-check (LDPC) repository, an LDPC code configurator, and LDPC decoding circuitry. The LDPC repository stores parity-check information associated with one or more LDPC codes. The LDPC code configurator may receive a first LDPC configuration describing a parity-check matrix for a first LDPC code and may update the parity-check information in the LDPC repository to reflect the parity-check matrix for the first LDPC code. The LDPC decoding circuitry may receive a first codeword encoded in accordance with the LDPC code. More specifically, the LDPC decoding circuitry may be configured to read the parity-check information associated with the first LDPC code from the LDPC repository and iteratively decode the first codeword using the parity-check information associated with the first LDPC code.

Abstract: Some examples described herein relate to routing in routing elements (e.g., switches). In an example, a design system includes a processor and a memory, storing instruction code, coupled to the processor. The processor is configured to execute the instruction code to model a communication network among switches interconnected in an array of data processing engines (DPEs), generate routes for an application on the modeled communication network, and translate the routes to a file. Each DPE includes a hardened processor core, a memory module, and one or more of the switches. Each switch includes an input or output port that is capable of being shared by multiple routes. Port(s) of each switch are modeled as respective node(s). Generating the routes includes using an A* algorithm that includes a congestion costing function based on a capacity of respective nodes in the modeled communication network and a cumulative demand for the respective nodes.

Abstract: Disclosed approaches for processing a circuit design include interrupting processing of a circuit design by an electronic design automation (EDA) tool at a selected phase of processing. The tool serializes EDA state data into serialized state data while processing is interrupted and writes the serialized state data for subsequent restoration of tool state. To resume processing at the point of interruption, the EDA tool can read the serialized state data and deserialize the serialized state data. The EDA tool bypasses one or more phases of processing after reading the serialized state data and thereafter resumes processing of the circuit design.

Abstract: Examples described herein generally relate to a Peripheral Connect Interconnect Express (PCIe) device. An example is a non-transitory memory storing a representation of a design that is to be implemented on a programmable integrated circuit. The design includes a classifier module (CM), a message trap engine module (MTEM), and a configuration space. The CM is capable of receiving a PCIe message and is configured to determine whether the PCIe message is a PCIe Type 1 configuration transaction. The CM is configured to forward the PCIe message to an endpoint device and to the MTEM when the PCIe message is a non-PCIe Type 1 configuration transaction and the PCIe Type 1 configuration transaction, respectively. The MTEM is configured to virtualize a downstream port(s) of a virtual switch and maintain the configuration space. The MTEM is capable of accessing the configuration space in response to the PCIe message.

Abstract: A data processing system comprising: first and second network ports each operable to support a network connection configured according to one or more of a predetermined set of physical layer protocols; and a processor configured to, on a network message being formed for transmission to a network endpoint accessible over either of the first and second network ports: estimate the total time required to, for each of the predetermined set of physical layer protocols, negotiate a respective network connection and transmit the entire network message over that respective network connection; select the physical layer protocol having the lowest estimate of the total time required to negotiate a respective network connection and transmit the network message over that respective network connection; and configure at least one of the first and second network ports to use the selected physical layer protocol.