Abstract: An example method of placing kernels of an application in a data processing engine array (DPE) of a system on chip (SOC) includes obtaining a graph of the application having nodes representing the kernels and edges representing communication between the kernels, sorting the kernels based on runtime ratio associated with each of the kernels, processing the sorted kernels sequentially to place into partitions, determining an execution order of kernels in each of the partitions; and generating implementation data for the SOC for implementing the application therein based on the determined partitions and execution order for each of the partitions.

Abstract: In some examples, a system includes a clock source, a clock distribution network, and a plurality of clock generators. The clock source is configured to generate a global clocking signal. The clock distribution network is configured to fan out the global clocking signal to a plurality of loads. The plurality of clock generators is configured to receive the global clocking signal through the clock distribution network. Each clock generator of the plurality of clock generators is configured to generate a related clocking signal to the global clocking signal from the received global clocking signal. Each clock generator of the plurality of clock generators maybe configured to supply the global clocking signal or the related clocking signal to its respective load of the plurality of loads.

Abstract: A data processing system comprising: a host processing device supporting a host transport engine operable to establish one or more transport streams over a network with a remote peer, the host transport engine maintaining state for each transport stream; and device hardware comprising: a device application; a device transport engine operable to perform transport processing of a transport stream on behalf of the device application; wherein the host transport engine is configured to, on establishing a first transport stream for termination at the device application, pass sufficient state to the device transport engine so as to permit the device transport engine to perform transport processing of the first transport stream.

Abstract: Apparatus and associated methods relate to implementing an analog auxiliary clock and data recovery (CDR) path to provide a high bandwidth CDR in a transceiver that supports both PAM4 and NRZ signaling. In an illustrative example, the auxiliary CDR path may include a phase-frequency detector (PFD)-based phase-locked loop (PLL) and a phase detector (PD)-based PLL. When the PFD-based PLL is locked to a reference clock signal of the transceiver, the PFD-based PLL may be then disabled and the PD-based PLL may be then enabled. Implementing the auxiliary CDR path may advantageously enable the transceiver to implement much larger parts per million (ppm) acquisition and tracking, and thus enable the transceiver to advantageously support new standards such as Peripheral Component Interconnect Express (PCIe) 5.0 and PCIe 6.0, for example.

Abstract: A network interface device has in input. The input receives packets in accordance with a protocol and has at least one protocol header. The network interface has hardware which applies an artificial intelligence process to at least one of the protocol headers. This is used to provide an output which may, for example, indicate a risk associated with a packet.

Abstract: Disclosed approaches for guiding actions in processing a circuit design include a design tool identifying first violations of design checks and determining severity levels of the first violations. The design tool determines for each violation, suggested actions associated with the violation and presents on a display, first data indicative of the suggested actions in order of the severity levels of the first violations. The first data include selectable objects, and each selectable object has an associated executable procedure. The design tool can execute the procedure associated with one of the selectable objects in response to selection and modify the circuit design in response to execution of the procedure.

Abstract: A device may include a plurality of data processing engines. Each of the data processing engines may include a core and a memory module. The plurality of data processing engines may be organized in a plurality of rows. Each core may be configured to communicate with other neighboring data processing engines of the plurality of data processing engines by shared access to the memory modules of the neighboring data processing engines.

Abstract: Apparatuses and methods relating generally to reduction of allocation of external power and/or ground pins of a microelectronic device are disclosed. In one such apparatus, an external power input pin is configured for receiving an input supply-side power having an external supply voltage level higher than an internal supply voltage level and an external supply current level lower than an internal supply current level. An internal power plane circuit coupled to the external power input pin is configured to step-down a voltage from the external supply voltage level to the internal supply voltage level and to step-up a current from the external supply current level to the internal supply current level to provide an internal power source.

Abstract: Apparatus and associated methods relate to a logic circuit having a number of unit circuits performing buffering and data storage functionalities in parallel. In an illustrative example, a logic circuit may include N unit circuits for data storage and N?1 unit circuits for buffering. During a conversion cycle, only an ith unit circuit of the N unit circuits and an (i?1)th unit circuit of the N?1 unit circuits may be enabled. Output status of the ith unit circuit of the N unit circuits may be monitored to disable the ith unit circuit, and also enable an (i?1)th unit circuit of the N unit circuits and an (i?2)th unit circuit of the N?1 unit circuits. By performing buffering and data storage in parallel, propagation delays in the SAR logic circuit may advantageously be reduced, and thus, conversion time of a successive-approximation-register (SAR) analog-to-digital converter (ADC) may be advantageously reduced.

Abstract: Some examples described herein relate to a design system and a method for printed circuit board (PCB) design. In an example, a design system includes a processor and a memory coupled to the processor. The memory stores instruction code. The processor is configured to execute the instruction code to provide a workspace in a user interface in which a PCB design comprising multiple layers is capable of being created; provide a list of layout templates in the user interface; and provide an insert function, via the user interface, configured to insert a selected layout template of the list of layout templates into the workspace to be included in the PCB design. Each layout template of the list of layout templates is a tile layout that includes a layout component and metal lines that extend to one or more edges of the tile layout.

Abstract: An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array includes determining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC, and generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.

Abstract: Examples described herein provide for single event latch-up (SEL) mitigation techniques. In an example, a circuit includes a semiconductor substrate, a first transistor, a second transistor, and a ballast resistor. The semiconductor substrate comprises a p-doped region and an n-doped region. The first transistor comprises an n+ doped source region disposed in the p-doped region of the semiconductor substrate. The second transistor comprises a p+ doped source region disposed in the n-doped region of the semiconductor substrate. The p+ doped source region, the n-doped region, the p-doped region, and the n+ doped source region form a PNPN structure. The ballast resistor is electrically connected in series with the PNPN structure between a power node and a ground node.

Abstract: Apparatus and associated methods relate to maintaining a total current of a switch cell in a digital-to-analog converter at a controllable operating point by adjusting shunt current control signals applied to programmable shunt current sources in opposite polarity with respect to a tail current control signal applied to a programmable tail current source. In an illustrative example, the total current may flow through differential legs of a switch cell. The programmable shunt current sources may, for example, be configured to compensate for adjustments to the programmable tail current source. In an illustrative example, tail current and shunt currents may flow through a pair of cascode transistors. In various examples, controlling the programmable shunt current sources to compensate adjustments to the tail current source may, for example, permit controlled common mode voltage or operating point so as to reduce device voltage stress over a wider dynamic range of output voltages.

Abstract: An apparatus and method for generating a dense wavelength division and multiplexing (DWDM) optical stream in a photonic integrated circuit (PIC) is disclosed. An optical input source including a number (N) of optical channels (wavelengths) may be separated (de-interleaved) into multiple optical streams, each including a corresponding subset of the optical channels of the optical input source. Each of the multiple split optical streams may be modulated with an associated set of data streams by silicon-based micro-ring modulators to generate a corresponding modulated optical stream. A first pair of the modulated optical streams may be combined (interleaved) to generate a first optical output stream including N/2 modulated optical channels, and a second pair of the modulated optical streams may be combined (interleaved) to generate a second optical output stream including N/2 modulated optical channels.

Abstract: A method for testing on-die capacitors is provided. The method comprises transmitting, during a first time period, a first modulated testing signal from a first transmitter port of a transmitter to a first receiver port of a receiver along a first path of a differential signal, the first receiver port connected to a first on-die capacitor in the receiver along the first path; driving, during the first time period, a constant voltage on a second transmitter port of the transmitter to a second receiver port of the receiver along a second path of the differential signal comprising a second on-die capacitor; and determining whether the first on-die capacitor is functional, based on the first modulated testing signal.

Abstract: A network device includes a plurality of ports, a lookup circuit, and a traffic control circuit. The lookup circuit is configured to provide a first action for a first frame to be forwarded using a first forwarding path between a first set of two ports of the plurality of ports. The lookup circuit is further configured to and provide a second action for a second frame to be forwarded using a second forwarding path between a second set of two ports of the plurality of ports. The traffic control circuit configured to forward the first frame based on the first action and forward the second frame based on the second action.

Abstract: Examples herein describe a method for memory address mapping. In one embodiment, the method includes selecting a bank group subset of bits from a plurality of bits that represent a memory address; selecting a bank address subset of bits from the plurality of bits; selecting a column subset of bits from the plurality of bits, wherein the column subset of bits is exclusive from the bank group subset of bits and the bank address subset of bits; and generating an optimal memory address mapping for converting system memory addresses into the plurality of local memory addresses for the memory banks using the bank group subset of bits, the bank address subset of bits, and the column subset of bits.

Abstract: Some examples described herein provide for clock tree generation for a programmable logic device, and more specifically, for clock tree generation in conjunction or simultaneous with placement of logic for a programmable logic device. In an example, a design system includes a processor and a memory coupled to the processor. The memory stores instruction code. The processor is configured to execute the instruction code to: generate clock trees in conjunction with placing logic for an application to be implemented in a programmable logic region of a programmable logic device; generate data routes between the placed logic; and generate a physical implementation of the application based on the placed logic, the clock trees, and the data routes. The physical implementation is capable of being loaded on the programmable logic region of the programmable logic device.

Abstract: A device includes a plurality of memory components with redundant columns associated therewith, a sub-block controller, and a volatile memory. The sub-block controller generates a repair vector, during manufacture testing mode. The repair vector is associated with the plurality of memory components and is generated responsive to detecting a defect within a column of the plurality of memory components. No repair vector is generated responsive to detecting no defect within a column of the plurality of memory components. The volatile memory receives and stores the repair vector in a nonvolatile memory component, during the manufacture testing mode. The volatile memory receives the repair vector from the nonvolatile memory component if the repair vector was generated during the manufacture testing mode, at startup mode, and provides it to the sub-block controller. The sub-block controller loads a repair data into the plurality of memory components based on the repair vector.

Abstract: Examples herein describe an accelerator device that shares the same coherent domain as hardware elements in a host computing device. The embodiments herein describe a mix of hardware and software coherency which reduces the overhead of managing data when large chunks of data are moved from the host into the accelerator device. In one embodiment, an accelerator application executing on the host identifies a data set it wishes to transfer to the accelerator device to be processed. The accelerator application transfers ownership from a home agent in the host to the accelerator device. A slave agent can then take ownership of the data. As a result, any memory operation requests received from a requesting agent in the accelerator device can gain access to the data set in local memory via the slave agent without the slave agent obtaining permission from the home agent in the host.