Abstract: Multi-domain creation and isolation within a heterogeneous System-on-Chip (SoC) may include receiving a hardware description file specifying a plurality of processors and a plurality of hardware resources available within a heterogeneous SoC and creating, using computer hardware, a plurality of domains for the heterogeneous SoC, wherein each domain includes a processor selected from the plurality of processors and a hardware resource selected from the plurality of hardware resources. The method may include assigning, using the computer hardware, an operating system to each domain and generating, using the computer hardware, a platform that is configured to implement the plurality of domains within the heterogeneous SoC.

Abstract: Some examples described herein relate to global mapping of program nodes of a netlist of an application. In an example, a design system includes a processor and a memory coupled to the processor. The memory stores instruction code. The processor is configured to execute the instruction code to obtain a netlist of an application. The netlist contains program nodes and respective edges between the program nodes. The application is to be implemented on a device comprising an array of data processing engines. The processor is also configured to execute the instruction code to generate a global mapping of the program nodes based on a representation of the array of data processing engines and using an integer linear programming (ILP) algorithm; generate a detailed mapping of the program nodes based on the global mapping; and translate the detailed mapping to a file.

Abstract: A circuit for memory access includes a memory access control circuit. The memory access controller is coupled to a memory and configured to perform data transfers to retrieve data from the memory. The memory access control circuit includes a timing control circuit and a transfer control circuit. The timing control circuit is configured to determine first timing information based on a timing requirement for transmitting a first data stream to a first network; and determine a first fetch time for retrieving the first data stream from the memory based on the first timing information. The transfer control circuit is configured to retrieve the first data stream from the memory based on the first fetch time.

Abstract: For an application having a software portion for implementation in a data processing engine (DPE) array of a device and a hardware portion for implementation in programmable logic (PL) of the device, an implementation flow is performed, using a processor executing a hardware compiler, on the hardware portion based on an interface block solution that maps logical resources used by the software portion to hardware of an interface block coupling the DPE array to the PL. In response to not meeting a design metric during the implementation flow, an interface block constraint is provided from the hardware compiler to a DPE compiler. In response to receiving the interface block constraint, an updated interface block solution is generated, using the processor executing the DPE compiler, and provided from the DPE compiler to the hardware compiler.

Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion having High-Level Synthesis (HLS) kernels for implementation within programmable logic (PL) of the device, a first interface solution is generated that maps logical resources used by the software portion to hardware resources of an interface block coupling the DPE array and the PL. A connection graph specifying connectivity among the HLS kernels and nodes of the software portion to be implemented in the DPE array; and, a block diagram based on the connection graph and the HLS kernels are generated. The block diagram is synthesizable. An implementation flow is performed on the block diagram based on the first interface solution. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.

Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion for implementation within programmable logic (PL) of the device, a logical architecture for the application and a first interface solution specifying a mapping of logical resources to hardware of an interface circuit block between the DPE array and the programmable logic are generated. A block diagram of the hardware portion is built based on the logical architecture and the first interface solution. An implementation flow is performed on the block diagram. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.

Abstract: An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array includes determining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC, and generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.

Abstract: Examples herein describe techniques for generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges (e.g., the communication links between the kernels). A compiler converts the source code into a bit stream and/or binary code which configure a heterogeneous processing system of a SoC to execute the graph. The compiler uses the graph expressed in source code to determine where to assign the kernels in the heterogeneous processing system. Further, the compiler can select the specific communication techniques to establish the communication links between the kernels and whether synchronization should be used in a communication link. Thus, the programmer can express the dataflow graph at a high-level (using source code) without understanding about how the operator graph is implemented using the heterogeneous hardware in the SoC.

Abstract: A capacitor includes a first metal layer over a substrate, a second metal layer over the first metal layer, and first and second cells. Each cell is electrically coupled to first and second buses. Each cell includes first plurality and second plurality of fingers in the first metal layer, and third plurality and fourth plurality of fingers in the second metal layer. The first plurality of fingers extend in a first direction parallel to a top surface of the substrate and are electrically coupled to the first bus. The second plurality of fingers extend in the first direction and are electrically coupled to the second bus. The third plurality of fingers extend in a second direction parallel to the top surface of the substrate and are electrically coupled to the first bus. The second direction is different from the first direction. The fourth plurality of fingers extend in the second direction and are electrically coupled to the second bus.

Abstract: Approaches for encoding include inputting a time-ordered sequence of source data to a machine learning (ML) encoder circuit. The ML encoder circuit extracts first features from a first subset of the source data and generates an ML model from the first features. The ML encoder circuit outputs the first subset of source data while generating the ML model and the ML model is incomplete. Once completed, the ML encoder circuit outputs the ML model for decoding subsequently extracted features. Thereafter, the ML encoder circuit extracts second features from a second subset of the source data and outputs the second features for decoding using the ML model.

Abstract: A design tool executing on a computer system converts a block model of a circuit design to a high-level language (HLL) specification. The design tool then converts the HLL specification to a hardware description language (HDL) specification. Circuit implementation data is generated from the HDL specification by the design tool, and the circuit implementation data can be used to make an integrated circuit that performs functions specified by the circuit design.

Abstract: Apparatus and associated methods relate to providing a regulation loop using a digital representation of a loop error signal along with a flexible multiplying capacitive digital-to-analog converter (MC-DAC) circuit to control one or more power switches (e.g., transistors) delivering required power (including voltage and/or current) to a load circuit. In an illustrative example, the MC-DAC circuit may include a digital-to-analog converter (DAC) configured to selectively couple to two different reference voltages in response to switch control signals generated by a digital filter. A capacitive level shifter may be coupled to the output of the DAC. A re-sampling circuit may be coupled to the output of the capacitive level shifter to generate a gate control signal to control the one or more power switches. The regulation loop may advantageously generate the gate control signal using a substantially reduced die area.

Abstract: A network interface device capable of communication with a data processing system supporting an operating system and at least one application, the network interface device supporting communication with the operating system by means of: two or more data channels, each data channel being individually addressable by the network interface device and being capable of carrying application-level data between the network interface device and the data processing device; and a control channel individually addressable by the network interface device and capable of carrying control data between the network interface device, the control data defining commands and the network interface being responsive to at least one command sent over the control channel to establish at least one additional data channel.

Abstract: A network interface device has an input configured to receive data from a network. The data is for one of a plurality of different applications. The network interface device also has at least one processor configured to determine which of a plurality of available different caches in a host system the data is to be injected by accessing to a receive queue comprising at least one descriptor indicating a cache location in one of said plurality of caches to which data is to be injected, wherein said at least one descriptor, which indicates the cache location, has an effect on subsequent descriptors of said receive queue until a next descriptor indicates another cache location. The at least one processor is also configured to cause the data to be injected to the cache location in the host system.

Abstract: An example programmable integrated circuit (IC) includes a processor, a plurality of endpoint circuits, a network-on-chip (NoC) having NoC master units (NMUs), NoC slave units (NSUs), NoC programmable switches (NPSs), a plurality of registers, and a NoC programming interface (NPI). The processor is coupled to the NPI and is configured to program the NPSs by loading an image to the registers through the NPI for providing physical channels between NMUs to the NSUs and providing data paths between the plurality of endpoint circuits.

Abstract: An example method for compiling by a processor-based system includes obtaining a netlist of an application, the netlist containing program nodes and respective edges between the program nodes, the application to be implemented on a device comprising an array of data processing engines; generating a global mapping of the program nodes based on a representation of the array of data processing engines; generating a detailed mapping of the program nodes based on the global mapping, the detailed mapping assigning input/outputs of programmable logic (PLIOs) of the device to channels in an interface of the array of data processing engines, the detailed mapping further assigning buffers of the application to individual memory banks in the array of data processing engines; and translating the detailed mapping to a file.

Abstract: A device includes a first and a second stage round robin arbitrations. The first stage receives request signals and selects a subset the request signals. Each request signal is associated with whether a component is requesting access to a common resource. The second stage receives the selected subset and grants access to the common resource to each request signal of the selected subset that is requesting access, in a round robin fashion. The second stage outputs an enable signal to the first stage when the selected subset is processed. The first stage selects another subset and transmits the selected another subset to the second stage for round robin processing thereof. The process is repeated until all subsets with at least one request signal to access the common resource is processed and granted access in a round robin fashion.

Abstract: A chip package assembly and method for fabricating the same are provided which utilize a stiffener to improve a package substrate against out of plane deformation. In one example, a chip package assembly is provided that includes a package substrate, at least one integrated circuit (IC) die and a stiffener. The package substrate has a first surface and a second surface coupled by a side wall. The at least one IC die is disposed on the first surface of the package substrate. The stiffener is disposed outward of the at least one IC die. The stiffener has a first surface disposed outward of and bonded to the side wall of the package substrate. The stiffener has a second surface bonded to at least one of the first and second surfaces of the package substrate.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for performing post-routing and post-placement physical synthesis optimizations. One of the methods includes receiving a circuit design of a multi-die integrated circuit (IC) device having a first die connected with a second die, wherein the circuit design specifies a respective initial component placement of each of a plurality of components on the first die and the second die. A first driver on the first die having a plurality of loads on the second die is selected. A transmit site is selected on the first die that reduces a distance between the first driver and a load of the plurality of loads on the second die. The circuit design is modified including moving the first driver to the selected transmit site on the first die.

Abstract: Examples described herein provide for testing of a test socket using multiple insertions to a contact resistance (CRES) test system. In an example, the test socket is placed in a first orientation on an interface board electrically connected to a test system. Using the test system and through the interface board, a first subset of probes of the test socket is tested while the test socket is in the first orientation on the interface board. The test socket is placed in a second orientation different from the first orientation on the interface board. Using the test system and through the interface board, a second subset of probes of the test socket is tested while the test socket is in the second orientation on the interface board. At least some probes of the second subset of probes are different from the first subset of probes.