Abstract: An integrated circuit device having a plurality of stacked dies is described. The integrated circuit device comprises a first die of the plurality of stacked dies having an input/output element configured to receive an input signal, the first die comprising a signal driver circuit configured to provide the input signal to each die of the plurality of stacked dies and a chip select circuit for generating a plurality of chip select signals for the plurality of stacked dies; and a second die of the plurality of stacked dies coupled to the first die, the second die having a function block configured to the receive the input signal; wherein the second die receives the input signal in response to a chip select signal of the plurality of chip select signals that corresponds to the second die. A method of implementing an integrated circuit device having a plurality of stacked dies is also described.

Abstract: A decoder circuit includes a low-density parity-check (LDPC) repository to store parity-check information associated with one or more LDPC codes and an LDPC code configurator to receive a first LDPC configuration describing a parity-check matrix for a first LDPC code and to update the parity-check information in the LDPC repository to reflect the parity-check matrix for the first LDPC code. The decoder circuit further includes an LDPC decoder circuitry configurable, based on control signals, to perform LDPC decoding of codewords or LDPC encoding of information using the parity-check information from the LDPC repository.

Abstract: A platform design including a module black-box instance is loaded into computer hardware. Using the computer hardware, synchronous boundary crossings between a static region and the module black-box instance of the platform design are identified and objects of the platform design included in the synchronous boundary crossings are marked. Using the computer hardware, unmarked objects are removed from the platform design to generate a shell circuit design. A custom circuit design is implemented based on the shell circuit design and timing constraints corresponding to objects remaining in the shell circuit design.

Abstract: A hash content addressable memory system includes a hash content addressable memory block (HCB) that is a physical subsystem of the hash content addressable memory system. The first HCB include first bus select logic. The first bus select logic is connected to a plurality of key buses and to a plurality of operation buses. Each key bus from the plurality of key buses and each operation bus from the plurality of operation buses is connected to one and only one client in a plurality of clients. Every client in the plurality of clients is connected to only one key bus from the plurality of key buses and is connected to only one operation bus from the plurality of operation buses.

Abstract: An optical receiver circuit is disclosed, including a photodiode, an output terminal, a first amplifier stage, and an electrostatic discharge (ESD) protection circuit. The photodiode may generate a receiver current based on received optical signals. The first amplifier stage may be coupled between the photodiode and the output terminal and include a first inductor coupled between the photodiode and an input of a first inverter, and a second inductor coupled between the input of the first inverter and a first resistor. The first resistor may be coupled between the second inductor and an output of the first inverter. ESD protection circuit may be coupled to the input of the first inverter. The output terminal may generate an output signal based at least in part on the output of the first inverter.

Abstract: A circuit arrangement includes one or more input buffers disposed on a system-on-chip (SoC) and configured to receive and store streaming debug packets. One or more response buffers are also disposed on the SoC. A transaction control circuit is disposed on the SoC and is configured to process each debug packet in the one or more input buffers. The processing includes decoding an operation code in the debug packet, and determining from an address in the debug packet, an interface circuit of multiple interface circuits to access a storage circuit in a subsystem of multiple sub-systems on the SoC. The processing further includes issuing a request via the interface circuit to access the storage circuit according to the operation code, and storing responses and data received from the interface circuits in the one or more response buffers.

Abstract: Apparatus and associated methods relate to adapting a continuous time linear equalization circuit with minimum mean square error baud-rate clock and data recovery circuit to be able to lock to the center or near center of an eye diagram. In an illustrative example, a circuit may include an inter-symbol interference (ISI) detector configured to receive data and error samples, a summing circuit coupled to the output of the ISI detector, a moving average filter configured to receive the output of the summing circuit and generate an average output, a voter configured to generate a vote in response to the average output and a predetermined threshold, and, an accumulator and code generator configured to generate a code signal in response to the generated vote. By introducing the moving average filter and the voter, a quicker way to lock to the center or near center of an eye diagram may be obtained.

Abstract: Approaches for folding multiply-and-accumulate (MAC) logic in a circuit design involve a design tool recognizing a first instance of the MAC logic and a second instance of the MAC logic. The design tool replaces the first instance of the MAC logic and the second instance of the MAC logic with one instance of pipelined MAC logic. The design tool configures the pipelined MAC logic to input data signals of the first instance of the MAC logic and the second instance of the MAC logic to the pipelined MAC logic at a first clock rate, and switch between selection of the data signals of the first instance of the MAC logic and the second instance of the MAC logic at a second clock rate that is double the first clock rate. The design tool further configures the pipelined MAC logic to pipeline input data signals at the second clock rate, and to capture intermediate results at the second clock rate. The design tool further configures a register to capture output of the pipelined MAC logic at the first clock rate.

Abstract: Examples herein describe a method for a compiler and hardware-abstraction-layer architecture for a programmable integrated circuit (IC). In one embodiment, a method for mapping and porting a neural network to an integrated circuit (IC) is disclosed. The method includes receiving a network description of the neural network; generating a framework independent network graph based on the network description; performing a plurality of back-end operations on the network graph to generate an execution sequence vector; and configuring the IC based on the execution sequence vector.

Abstract: Apparatus and associated methods relate to unit circuits that having a number of capacitors and/or buffers controlled by two different control signals, capacitors and/or buffers that receiving, through routing, a same control signal from a control circuit are physically placed adjacent without crossing routings that connects capacitors and/or buffers controlled by a different control signal. In an illustrative example, a first capacitor may be configured to receive a first control signal through an inverting buffer, and a second capacitor may be configured to receive the first control signal through a non-inverting buffer, the inverting buffer and the non-inverting buffer may be provided by an integrated buffer structure. By arranging the physical positions of the capacitors and/or buffers, wire capacitances of the unit circuit may be advantageously reduced.

Abstract: An electronic device and method for fabricating the same are disclosed herein. In one example the electronic device includes a substrate, a first die stack, and a second die stack. The first die stack includes a first functional die and a first dummy die. The first functional die is mounted to the substrate. The second stack includes a plurality of serially stacked second functional dies mounted to the substrate. The first dummy die is stacked on the first functional die. The first dummy die has a top surface that is substantially coplanar with a top surface of the second die stack. In one particular example, the first die stack includes a logic die and the second die stack includes a plurality of serially stacked memory dies.

Abstract: Apparatus and associated methods relating to reducing lock time include pre-calibrating and storing phase-locked loop (PLL) and/or injection-locked oscillator (ILO) adaptation values during startup and loading the pre-calibrated values during rate change. In an illustrative example, an integrated circuit may include a controllable frequency circuit operable at frequencies within each of a plurality of frequency bands. A data store may store operational settings associated with each frequency of the plurality of frequency bands. A state machine may be coupled to the controllable frequency circuit and the data store configured to select a predetermined frequency band in response to a command signal, retrieve, from the data store, operational settings associated with the predetermined frequency band, and, apply the retrieved operational settings to the controllable frequency circuit.

Abstract: An example method for compiling includes, by a processor-based system: obtaining a netlist of an application, the netlist containing program nodes and respective edges between the program nodes, the application to be implemented on a device comprising an array of data processing engines; partitioning the netlist into a plurality of partitions; for each of the plurality of partitions: generating a global mapping of the program nodes based on a representation of the array of data processing engines and using an integer linear programming (ILP) algorithm; generating a detailed mapping of the program nodes based on the global mapping; and translating the detailed mapping for each of the plurality of partitions to a file.

Abstract: A signature is generated to indicate a direct memory access (DMA) operation involving a transfer, by a DMA engine, of data between a host memory circuit and an endpoint memory circuit of an endpoint processor circuit. First descriptors of the DMA engine are defined relative to the endpoint memory circuit or host memory circuit. A signature is received that indicates that second descriptors have been configured by the endpoint processor circuit. In response to receiving the endpoint signature, the DMA engine is enabled to begin the DMA operation.

Abstract: Methods and apparatus are described for adding one or more features (e.g., high bandwidth memory (HBM)) to an existing qualified stacked silicon interconnect (SSI) technology programmable IC die (e.g., a super logic region (SLR)) without changing the programmable IC die (e.g., adding or removing blocks). One example integrated circuit (IC) package generally includes a package substrate; at least one interposer disposed above the package substrate and comprising a plurality of interconnection lines; a programmable IC die disposed above the interposer; a fixed feature die disposed above the interposer; and an interface die disposed above the interposer and configured to couple the programmable IC die to the fixed feature die using a first set of interconnection lines routed through the interposer between the programmable IC die and the interface die and a second set of interconnection lines routed through the interposer between the interface die and the fixed feature die.

Abstract: An example hardware accelerator for a computer system includes a programmable device and further includes kernel logic configured in a first programmable fabric of the programmable device, a shell circuit configured in a second programmable fabric of the programmable device, the shell circuit configured to provide an interface between a computer system and the kernel logic, and an intellectual property (IP) checker circuit in the kernel logic The IP checker circuit is configured to obtain a device identifier (ID) from the first programmable fabric and a signed whitelist, the signed whitelist including a list of device IDs and a signature, verify the signature of the signed whitelist, compare the device ID against the list of device IDs, and selectively assert or deassert an enable of the kernel logic in response to presence or absence, respectively, of the device ID in the list of device IDs and verification of the signature.

Abstract: A circuit arrangement for calibrating a circuit in an integrated circuit device is described. The circuit arrangement may comprise a main circuit configured to receive input data at a first input and generate output data at a first output, wherein the output data is based upon the input data and a function of the main circuit; a replica circuit configured to receive calibration data at a second input and generate calibration output data, based upon the calibration data, at a second output, wherein the replica circuit provides a replica function of the function of the main circuit; and a calibration circuit configured to receive the output data from the main circuit during a foreground calibration mode, and the calibration output data from the replica circuit during a background calibration mode; wherein the calibration circuit provides control signals to the main circuit during the background calibration mode. A method of calibrating a circuit in an integrated circuit device is also described.

Abstract: An example hardware accelerator for a computer system includes a programmable device and further includes kernel logic configured in a programmable fabric of the programmable device, and an intellectual property (IP) checker circuit in the kernel logic. The IP checker circuit is configured to obtain a device identifier (ID) of the programmable device and a signed whitelist, the signed whitelist including a list of device IDs and a signature, verify the signature of the signed whitelist, compare the device ID against the list of device IDs, and selectively assert or deassert an enable of the kernel logic in response to presence or absence, respectively, of the device ID in the list of device IDs and verification of the signature.

Abstract: Protecting circuit designs can include, in response to receiving a first encrypted public key, generating, using a hash circuit within the integrated circuit, a first hash of the first encrypted public key. The first hash can be compared with a second hash that was previously stored within a non-volatile memory of the integrated circuit. In response to determining that the first hash matches the second hash, the first encrypted public key is decrypted resulting in a first decrypted public key. A determination is made whether received configuration data for the device is authentic using the first decrypted public key.

Abstract: Apparatus and associated methods relate to high accuracy timestamp support by controlling a first phase relationship between an outbound signal transmitted by a transmitting circuit and a local reference clock signal, measuring a second phase difference between a received data signal and the local reference signal, and measuring a third phase difference between a received time of day (RXTOD) signal and the local reference signal. In an illustrative example, a state machine circuit may be operated to control the first phase relationship, a phase measuring circuit may be configured to measure the second phase difference and the third phase difference. By comparing results obtained from phase control and phase measurement, the time of day (TOD) of each transmitted/received bit can be calculated at 1-bit level accuracy and achieve 1-bit level accuracy in the timestamp.