Abstract: A phase locked loop (PLL) circuit includes a voltage controlled oscillator (VCO), a first loop circuit, and a second loop circuit. The first loop circuit includes a first loop filter configured to receive a first signal based on a feedback signal from the VCO and provide a first VCO frequency control signal to the VCO. The second loop circuit includes a compensation circuit configured to receive a reference signal and the first signal, and provide a second VCO frequency control signal to the VCO.

Abstract: Examples of the present disclosure provide example Chip Scale Packages (CSPs). In some examples, a structure includes a first integrated circuit die, a shim die that does not include active circuitry thereon, an encapsulant at least laterally encapsulating the first integrated circuit die and the shim die, and a redistribution structure on the first integrated circuit die, the shim die, and the encapsulant. The redistribution structure includes one or more metal layers electrically connected to the first integrated circuit die.

Abstract: An electronic device and method for fabricating the same are disclosed herein. In one example the electronic device includes a substrate, a first die stack, and a second die stack. The first die stack includes a first functional die and a first dummy die. The first functional die is mounted to the substrate. The second stack includes a plurality of serially stacked second functional dies mounted to the substrate. The first dummy die is stacked on the first functional die. The first dummy die has a top surface that is substantially coplanar with a top surface of the second die stack. In one particular example, the first die stack includes a logic die and the second die stack includes a plurality of serially stacked memory dies.

Abstract: Apparatus and associated methods relate to a clock generation circuit which generates asynchronous clock signals for a successive approximation ADC architecture based on time-interleaved comparators. In an illustrative example, a circuit may include (a) a first comparator configured to receive an input signal and generate a first ready signal to indicate a comparison decision being complete, (b) a second comparator configured to receive the input signal and generate a second ready signal to indicate a comparison decision being complete, and (c) a clock generation circuit coupled to receive the first and the second ready signals and generate a first clock for the first comparator and a second clock for the second comparator. The first and the second clock signals may be in anti-phase. Thus, each comparator may have enough time to reach a valid comparison in each successive approximation cycle, and kickback noises at comparator' inputs may be advantageously reduced.

Abstract: Circuits and methods for combined precise and imprecise snoop filtering. A memory and a plurality of processors are coupled to the interconnect circuitry. A plurality of cache circuits are coupled to the plurality of processor circuits, respectively. A first snoop filter is coupled to the interconnect and is configured to filter snoop requests by individual cache lines of a first subset of addresses of the memory. A second snoop filter is coupled to the interconnect and is configured to filter snoop requests by groups of cache lines of a second subset of addresses of the memory. Each group encompasses a plurality of cache lines.

Abstract: A chip package assembly and method for fabricating the same are provided which utilize a composite stiffener selected to provide excellent resistance to warpage without detrimentally imposing excessive stress on a package substrate of the package assembly. In one example, the chip package assembly includes an integrated circuit die stacked on a top surface of a package substrate, and a composite stiffener coupled to a first edge of the package substrate. The composite stiffener includes a first stiffener member and a second stiffener member. The first stiffener member has a bottom surface bonded to the top surface of the package substrate. The second stiffener member is disposed over the first stiffener member. The second stiffener member has a bottom surface bonded to the top surface of the package substrate. The second stiffener member has a Young's modulus that is less than a Young's modulus of the first stiffener member.

Abstract: Examples described herein provide for a boundary logic interface (BLI) to a programmable logic region in an integrated circuit (IC), and methods for operating such IC. An example IC includes a programmable logic region and boundary logic interfaces. The programmable logic region includes columns of interconnect elements disposed between columns of logic elements. The boundary logic interfaces are at respective ends of and communicatively connected to the columns of interconnect elements. The boundary logic interfaces are outside of a boundary of the programmable logic region. A first boundary logic interface (BLI) of the boundary logic interfaces is configured to be communicatively connected to an exterior circuit. The first BLI includes an interface configured to communicate a signal between the exterior circuit and the programmable logic region.

Abstract: An example clock synthesizer, having a single-phase clock signal as input and generating an output clock, includes a phase decrementer configured to receive a fractional period value, configured to, responsive to the fractional period value, maintain a fractional count, and configured to accumulate residual phase from cycle-to-cycle of the output clock. A clock generator provides an integer-count-zero signal indicative of an integer portion of the fractional count reaching zero. A clock phase selector is configured to provide a signal having a fractional portion of the fractional count. A phase generator and combiner is coupled to an output of the clock generator, and an output of the clock phase selector, and is configured to provide the output clock.

Abstract: Using a high-level language (HLL) callable library for multiple instances of a core includes detecting, using computer hardware, a reference to an HLL library for a core within an HLL application, determining, using the computer hardware, a plurality of instances of the core by detecting function calls within the HLL application correlated to each of the plurality of instances of the core, and generating, using the computer hardware, interface code within the HLL application for each of the plurality of instances of the core using the HLL library. An executable version of the HLL application is generated, using the computer hardware, wherein the interface code for each of the plurality of instances of the core is bound to the respective instance of the core. The function calls can specify different parameterization files corresponding to the plurality of instances of the core.

Abstract: Embodiments herein describe techniques for binning integrated circuits (ICs) using an adaptive binning system that can re-bin the ICs in response to receiving a new or updated test specification. Unlike static binning systems, in one embodiment, the binning system receives measured test data from a testing system. Put differently, instead of a testing apparatus simply indicating whether an IC does (or does not) satisfy the criteria in the test specification, the testing apparatus provides measured test data to the binning system. The binning apparatus can then store the received test data. As such, if a new test specification is received or generated, the binning system can use the already saved test data to re-bin the ICs using the criteria in the new test specification without having to re-test the ICs. In this manner, the binning system can re-categorize the ICs as customer needs or customer demand changes.

Abstract: A method includes inputting to a computer processor a search value. Bit values of bit element signals of a bus at a current time are determined time-ordered value pairs of timestamps and associated bit values of the bit element signals. Whether the bit values at the current time match values of corresponding bits of the search value is determined from the time-ordered value pairs. Data indicative of the current time and bit values of the bit element signals is output if the bit values at the current time match the search value. If any of the bit values at the current time do not match the search value, the current time is advanced to a later time indicated by a time-ordered value pair not matched to the search value and having a latest timestamp of the bit element signals that do not match corresponding bits of the search value.

Abstract: Examples described herein provide for a boundary logic interface (BLI) to a programmable logic region in an integrated circuit (IC), and methods for operating such IC. An example IC includes a programmable logic region and boundary logic interfaces. The programmable logic region includes columns of interconnect elements disposed between columns of logic elements. The boundary logic interfaces are at respective ends of and communicatively connected to the columns of interconnect elements. The boundary logic interfaces are outside of a boundary of the programmable logic region. A first boundary logic interface (BLI) of the boundary logic interfaces is configured to be communicatively connected to an exterior circuit. The first BLI includes an interface configured to communicate a signal between the exterior circuit and the programmable logic region.

Abstract: Roughly described: a network interface device has an interface. The interface is coupled to first network interface device circuitry, host interface circuitry and host offload circuitry. The host interface circuitry is configured to interface to a host device and has a scheduler configured to schedule providing and/or receiving of data to/from the host device. The interface is configured to allow at least one of: data to be provided to said host interface circuitry from at least one of said first network device interface circuitry and said host offload circuitry; and data to be provided from said host interface circuitry to at least one of said first network interface device circuitry and said host offload circuitry.

Abstract: A network interface device having an FPGA for providing an FPGA application. A first interface between a host computing device and the FPGA application is provided, allowing the FPGA application to make use of data-path operations provided by a transport engine on the network interface device, as well as communicate with the host. The FPGA application sends and receives data with the host via a memory that is memory mapped to a shared memory location in the host computing device, whilst the transport engine sends and receives data packets with the host via a second memory. A second interface is provided to interface the FPGA application and transport engine with the network, wherein the second interface is configured to back-pressure the transport engine.

Abstract: Creating a high-level language (HLL) callable library for a hardware core can include automatically querying, using computer hardware, a metadata description of a core to determine a plurality of available ports of the core, automatically determining, using the computer hardware, an argument of a first function specified in a header file corresponding to the core, mapping, using the computer hardware, the argument to a first port of the plurality of available ports, and automatically generating and storing, using the computer hardware, an HLL library specifying a mapping of the argument to the first port of the core. The HLL library is configured for inclusion with a user application during compilation.

Abstract: Examples described herein provide determining skew of transistors on an integrated circuit. In an example, an integrated circuit includes a ring oscillator and first and second detector circuits. The ring oscillator includes serially connected buffers. Each buffer includes serially connected inverters that include transistors. A transistor of each buffer has a different strength of another transistor of the respective buffer. The first and second detector circuits are connected to different first and second tap nodes, respectively, along the serially connected buffers. The first detector circuit is configured to count a number of cycles of a reference clock that a cyclic signal on the first tap node is either a logically high or low level. The second detector circuit is configured to count a number of cycles of the reference clock that a cyclic signal on the second tap node is either a logically high or low level.

Abstract: Apparatus and associated methods relate to a circuit that is configured to keep a comparator input voltage stable. In an illustrative example, the circuit may include a first differential path coupled to a first switched-capacitor network's output, a second differential path coupled to a second switched-capacitor network's output. A comparator may have a first input coupled to the first differential path and a second input coupled to the second differential path. The comparator may be controlled by a clock signal to perform comparison. A first capacitor may be coupled from the clock signal to the first differential signal path and a second capacitor may be coupled from the clock signal to the second differential signal path. By introducing the first capacitor and the second capacitor, the comparator input common-mode may keep stable, and the comparator may be less sensitive to kickback effects.

Abstract: A die-to-die interconnect structure includes an interconnect network including a plurality of metal interconnect layers. The interconnect network is configured to electrically couple a first die and a second die mounted on a top surface of the die-to-die interconnect structure. A first metal interconnect layer of the plurality of metal interconnect layers includes a plurality of ground lines and a plurality of signal lines distributed across the first metal interconnect layer according to a GSSG pattern. In some examples, adjacent signal lines within the first metal interconnect layer are separated by a dielectric region. In some embodiments, a second metal interconnect layer of the plurality of metal interconnect layers is disposed above the first metal interconnect layer and includes a plurality of configurable signal/ground lines. By way of example, each of the plurality of configurable signal/ground lines is disposed over the dielectric region and within the second metal interconnect layer.

Abstract: An execution circuit inputs a plurality of data units, performs unit operations on the data units, and registers results of the unit operations in response to oscillations of a clock signal. A control circuit controls activation of the unit operations, and outputs a start signal to the execution circuit to activate each unit operation and/or a completion signal to indicate completion of each unit operation. A debug circuit stores breakpoint flags associated with the unit operations. Each breakpoint flag has a state that specifies whether to stop oscillations of the clock signal. The debug circuit further receives the start and/or completion signal and evaluates, while the clock signal oscillates to the execution circuit, a state of the start and/or completion signal and a state of the breakpoint flag associated with the unit operation. Oscillations of the clock signal are stopped in response to the evaluation of the signals.

Abstract: Disclosed approaches involve at least one processor executing a program and a debug interface circuit coupled to the processor. The debug interface circuit is configured to transmit first trace data from the first processor. A debug access port is coupled to the debug interface circuit. A fault detection circuit is coupled to the debug access port and is configured to receive the first trace data via the debug access port and compare the first trace data to second data. The fault detection circuit generates an error signal to the first processor in response to a discrepancy between the first trace data and the second data.