Abstract: A system comprises a pair of configurable logic blocks (CLBs) placed adjacent to each other wherein each of the CLBs includes a plurality of configurable logic elements. A plurality sets of inodes are configured to accept signals to and/or from the CLBs, wherein a first set of inodes is positioned to the left of the adjacent CLBs and a second set of inodes is positioned to the right of the adjacent CLBs. A plurality of bnodes are embedded in the middle of the adjacent CLBs, wherein each bnode is configured to establish a first connection between the bnode and one of the first set of inodes on the left of the CLBs and a second connection between the bnode and one of the second set of inodes on the right of the CLBs. Both the first and second routing connections are localized within the pair of adjacent CLBs.

Abstract: Apparatus and associated methods relate to automatically generating a data structure representation of an on-chip inductive-capacitive (LC) tank circuit by determining parasitic inductances in each of the segments of conductive paths that connect a main inductor to one or more selectable VCO components such as capacitors and varactors, for example. In an illustrative example, one or more of the selectable VCO components may be arranged, when selected, to form a parallel resonant LC tank with the main inductor. A method may include defining nodes ai terminating each of the segments along the conductive paths between the main inductor terminals and a drive circuit. By modelling the paths as multi-port inductors and transformers, resonant frequency of the VCO may be more accurately predicted by simulation.

Abstract: Disclosed approaches for managing a translation look-aside buffer (TLB) have a bus master circuit that issues a read request that specifies a first virtual address of a first page. In response to a sequential access being identified and before data of the first page is returned, the bus master circuit issues a dummy read request that specifies a second virtual address of a second page. A TLB has mappings of virtual addresses to physical addresses, and a translation logic circuit translates virtual addresses to physical addresses. The translation logic circuit signals a miss in response to absence of a virtual address in the TLB. A control circuit in the MMU determines from a page table a mapping of a virtual address to a physical address in response to the signaled miss. The translation logic circuit updates the TLB circuit with the mapping.

Abstract: A data processing system comprising: an operating system providing an application programming interface; an application supported by the operating system and operable to make calls to the application programming interface; an intercept library configured to intercept calls of a predetermined set of call types made by the application to the application programming interface; and a configuration data structure defining at least one action to be performed for each of a plurality of sequences of one or more calls having predefined characteristics, the one or more calls being of the predetermined set of call types; wherein the intercept library is configured to, on intercepting a sequence of one or more calls defined in the configuration data structure, perform the corresponding action(s) defined by the configuration data structure.

Abstract: A network interface device comprises an integrated circuit device comprises at least one processor. A network interface device comprises a memory. The integrated device is configured to execute a function with respect to at least a part of stored data in said memory.

Abstract: Systems and methods for monitoring operating conditions of a programmable device are disclosed. The system may include a root monitor configured to generate a reference voltage, a plurality of sensors distributed across the device, and a plurality of satellite monitors distributed across the device. Each of the satellite monitors may be coupled to a corresponding sensor via a local interconnect, and may be configured to convert analog signals generated by the sensor into digital data indicative of one or more operating conditions of an associated circuit. In some implementations, each satellite monitor may include a circuit to store a local reference voltage, an analog-to-digital converter (ADC) to convert the analog signals into digital codes, a calibration circuit to generate a correction factor indicative of errors in the digital codes, and a correction circuit to correct the digital codes based on the correction factor.

Abstract: An integrated circuit (IC) can include a command queue having a plurality of slots corresponding to commands from a host processor for execution by a plurality of compute units of the IC and a command request register having a plurality of locations corresponding to the plurality of slots in the command queue. The command request register is configured to generate an interrupt indicating a new command stored within the command queue. The IC can include a controller configured to, in response to the interrupt from the command request register, determine a selected compute unit that is idle from the plurality of compute units to execute the new command. The IC can also include a compute unit direct memory access circuit configured to provide the new command to the available compute unit.

Abstract: An integrated circuit (IC) chip package assembly apparatus and techniques for assembling IC chip packages are described. For example, a techniques for fabricating an IC package include (A) determining a first package assembly yield (PAY) across a first die pool comprising a first plurality of dies having a performance criteria within a first predefined range; (B) determining a second PAY across a second die pool comprising a second plurality of dies having a performance criteria within a second predefined range of performance criteria that is different than the first predefined range of performance criteria, the second plurality of dies comprising a portion of the first plurality of dies; and (C) generating a final assembly sequence in response to analyzing the first and second PAYs, the final assembly sequence comprising rules for combining dies in accordance with obtaining a higher of the first PAY and the second PAY.

Abstract: Approaches for simulating and processing a circuit design involve recognizing by a design processing tool a replaceable subsystem in a circuit design having multiple blocks. The replaceable subsystem includes a subset of the blocks. The design tool converts the subset of blocks into an executable program and schedules activation of blocks of the circuit design other than the subset of blocks during simulation of the circuit design. The scheduled blocks are activated during simulation according to the scheduling, and activation of the subset of the plurality of blocks is bypassed during simulation with a call to the executable program.

Abstract: A rule engine receives data flows. The data flows are between a network and an application. The rule engine determines data flow information and in dependence on the information performs an action with respect to said flow. A controller provides control information to the rule engine to define one or more actions. The communications between said rule engine and said controller are secure.

Abstract: Examples herein describe a peripheral I/O device with a domain assist processor (DAP) and a domain specific accelerator (DSA) that are in the same coherent domain as CPUs and memory in a host computing system. Peripheral I/O devices were previously unable to participate in a cache-coherent shared-memory multiprocessor paradigm with hardware resources in the host computing system. As a result, domain assist processing for lightweight processor functions (e.g., open source functions such as gzip, open source crypto libraries, open source network switches, etc.) either are performed using CPUs resources in the host or by provisioning a special processing system in the peripheral I/O device (e.g., using programmable logic in a FPGA). The embodiments herein use a DAP in the peripheral I/O device to perform the lightweight processor functions that would otherwise be performed by hardware resources in the host or by a special processing system in the peripheral I/O device.

Abstract: Disclosed systems and methods include in each agent, an agent layer, a link layer, and a port layer. The agent layer looks-up a port identifier in an address-to-port identifier map in response to a request directed to another agent and submits the request to the port layer. The link layer includes a plurality of links, and each link buffers communications from and to the agent layer. The port layer looks-up, in response to the request from the agent layer, a link identifier and chip identifier and writes the request to one of the links identified by the link identifier and associated with the chip identifier. The port layer also reads requests from the links and submits communications to a transport layer circuit based on the requests read from the links and associated chip identifiers.

Abstract: Methods and apparatus for implementing a circuit design are provided. A physical description is generated corresponding to a predefined physical layout of a programmable integrated circuit. The circuit design includes a memory block. A timing analysis is executed to determine a first timing profile of the physical description. The physical description is optimized (or at least altered), and a physical implementation is generated based on the optimized physical description. Optimizing the physical description includes: selectively moving from or into the memory block of the physical description a register in response to an attribute of the memory block; executing a timing analysis to determine a second timing profile of the physical description with the register moved from or into the memory block of the physical description; comparing the first and second timing profiles; and selectively accepting or reversing the moving based on the comparison of the first and second timing profiles.

Abstract: Apparatus and method relates generally to data processing kernel. In such an apparatus, a datapath pipeline is configured to process datasets interlaced with respect to one another for multiple passes through a loop with conditional or data dependent decision points. A queue manager is configured with control circuitry sets to provide an instruction interface to the datapath pipeline. Each of the control circuitry sets includes: a first buffer and a second buffer each configured to buffer tokens for correspondence with the datasets. Each of the control circuitry sets further includes: an arbiter configured to decouple the conditional or data dependent decision points from the datapath pipeline to selectively provide access of the first buffer or the second buffer to the datapath functions. Memory is configured to provide access to and storage of the datasets to the datapath pipeline.

Abstract: The present invention relates to recurrent neural network. In particular, the present invention relates to how to implement and accelerate a recurrent neural network based on an embedded FPGA. Specifically, it proposes an overall design processing method of matrix decoding, matrix-vector multiplication, vector accumulation and activation function. In another aspect, the present invention proposes an overall hardware design to implement and accelerate the above process.

Abstract: A computer-implemented design flow can include, within a circuit design for an integrated circuit, determining a portion of the circuit design that is a candidate for implementation as a runtime customizable circuit and determining implementation options for the runtime customizable circuit. The design flow can also include generating, using computer hardware, a description of the circuit design using the runtime customizable circuit to implement the portion of the circuit design and generating, using the computer hardware, program code for an embedded processor coupled to an implementation of the runtime customizable circuit within the integrated circuit. The program code is usable by the embedded processor to parameterize the runtime customizable circuit to create a specific instance of the runtime customizable circuit.

Abstract: A system is arranged to receive data which is written to a data store by a writer. A controller is able to read data from the data store. That controller is able to control the rate at which data is read from the data store with respect to the rate at which data is written to the data store. A query function receives a stream of said data substantially in real time and when said stream of data is unavailable in real time, the query function is able to subsequently obtain that unavailable data from said data store.

Abstract: A chip package assembly and method for fabricating the same are provided which utilize at least one modular core dice to reduce the cost of manufacture. The modular core dice include at least two die disposed on a wafer segment that are separated by a scribe lane. In one example, a chip package assembly is provided that includes an interconnect substrate stacked below a first wafer segment. The first wafer segment has a first die spaced from a second die by a first scribe lane. The interconnect substrate has conductive routing that is electrically connected to the first die and the second die through die connections.

Abstract: Diagnosing applications that use hardware acceleration can include emulating, using a processor, a kernel designated for hardware acceleration by executing a device program binary implementing a register transfer level simulator for the kernel. The device program binary is executed in coordination with a host binary and a static circuitry binary. During the emulation, error conditions may be detected using diagnostic program code of the static circuitry binary. The error conditions may relate to memory access violations or kernel deadlocks. A notification of error conditions may be output.

Abstract: A radar system includes a transmitter to transmit a sequence of pulses, a receiver to receive reflections of the transmitted pulses, and velocity detection circuitry to determine a velocity of an object in a path of the transmitted pulses based at least in part on the transmitted pulses and the reflected pulses. The transmitter includes a plurality of digital-to-analog converters (DACs) to generate the sequence of pulses in response to a clock signal. The receiver includes a plurality of analog-to-digital converters (ADCs) to sample the reflected pulses in response to the clock signal. Accordingly, the ADCs are locked in phase with the DACs.