Abstract: A method for managing I/O event notifications in a data processing system comprising a plurality of applications and an operating system having a kernel and an I/O event notification mechanism operable to maintain a plurality of I/O event notification objects each handling a set of file descriptors associated with one or more I/O resources. For each of a plurality of application-level configuration calls: intercepting at a user-level interface a configuration call from an application to the I/O event notification mechanism for configuring an I/O event notification object; and storing a set of parameters of the configuration call at a data structure, each set of parameters representing an operation on the set of file descriptors handled by the I/O event notification object; and subsequently, upon meeting a predetermined criterion: the user-level interface causing the plurality of configuration calls to be effected by means of a first system call to the kernel.

Abstract: A method of transmitting data for use at a data processing system and network interface device, the data processing system being coupled to a network by the network interface device, the method comprising: forming a message template in accordance with a predetermined set of network protocols, the message template including at least in part one or more protocol headers; forming an application layer message in one or more parts; updating the message template with the parts of the application layer message; processing the message template in accordance with the predetermined set of network protocols so as to complete the protocol headers; and causing the network interface device to transmit the completed message over the network.

Abstract: Various implementations of a multi-chip system operable according to a predefined transport protocol are disclosed. In one embodiment, a system comprises a first IC comprising a processing element communicatively coupled with first physical ports. The system further comprises a second IC comprising second physical ports communicatively coupled with a first set of the first physical ports via first physical links, and one or more memory devices that are communicatively coupled with the second physical ports and accessible by the processing element via the first physical links. The first IC further comprises a data structure describing a first level of port aggregation to be applied across the first set. The second IC comprises a first distribution function configured to provide ordering to data communicated using the second physical ports. The first distribution function is based on the first level of port aggregation.

Abstract: Embodiments herein describe binning and placement techniques for assembling a multi-die device to improve yield when a customer requests a high performance feature from the device. For example, the multi-die device may include multiple dies that are interconnected to form a single device or package. In one embodiment, the multiple dies are the same semiconductor die (e.g., have the same circuit layout) which are disposed on a common interposer or stacked on each other. The multi-die device can then be attached to a printed circuit board (PCB). Although the dies in the multi-die device may each include the same feature (e.g., a PCIe interface, SerDes interface, transmitter, memory interface, etc.), the multi-die device is assembled so that not all of the dies have a feature that satisfies the high performance requested by the customer. That is, at least one of the die includes a lower performance feature.

Abstract: A chip package assembly is provided that includes a substrate, at least one integrated circuit (IC) die and a power management integrated circuit (PMIC). In one example, the IC die of the chip package assembly is disposed on a first surface of the substrate. The PMIC die has a first surface having outputs electrically coupled to the second surface of the IC die. The PMIC die also has a second surface facing away from the first surface. The second surface of the PMIC die has inputs that are electrically coupled to the first surface of the substrate.

Abstract: Disclosed approaches of pipelining cascaded memory blocks include determining memory blocks combined to implement a memory in a netlist of a circuit design. A model of the memory blocks arranged in a matrix is generated and a total number of delay registers that can be inserted between an input and an output of the memory is determined based on an input latency constraint. For each column, positions of delay registers are determined between an input of the column and the output of the memory. The circuit design is modified to include the delay registers at the determined positions.

Abstract: Apparatus and method relate generally to a configuration engine. In one such configuration engine for a programmable circuit, a frame counter includes a cascade of frame incrementer circuits associated with columns for a row of circuit blocks. Each frame incrementer circuit is configured to provide frame sums for frames associated with the circuit blocks. The frame counter is configured to sequentially add the frame sums for the columns to provide corresponding frame totals respectively for circuit types of the circuit blocks. A termination circuit is configured to multiplex the frame totals onto a data bus. A row controller is configured to initiate the frame counter and to selectively access the frame totals provided to the data bus.

Abstract: An integrated circuit (IC) can include a command queue having a plurality of slots corresponding to commands from a host processor for execution by a plurality of compute units of the IC and a command request register having a plurality of locations corresponding to the plurality of slots in the command queue. The command request register is configured to generate an interrupt indicating a new command stored within the command queue. The IC can include a controller configured to, in response to the interrupt from the command request register, determine a selected compute unit that is idle from the plurality of compute units to execute the new command. The IC can also include a compute unit direct memory access circuit configured to provide the new command to the available compute unit.

Abstract: An improved interconnect substrate having high density routings for a chip package assembly, a chip package assembly having a high density substrate, and methods for fabricating the same are provided that utilize substrates having a region of high density routings disposed over a region of low density routings. In one example, a method for fabricating an interconnect substrate is provided that includes forming a high density routing region by depositing a seed layer on a top surface of a low density routing region, patterning a mask layer on the seed layer, forming a plurality of conductive posts on the seed layer, removing the mask layer and the seed layer exposed between the conductive posts, and depositing a dielectric layer between the between the conductive posts, wherein at least some of the conductive posts are electrically coupled to conductive routing comprising the low density routing region.

Abstract: A circuit arrangement includes an encryption circuit and a decryption circuit. A cryptographic shell circuit has a transmit channel and a receive channel in parallel with the transmit channel. The transmit channel includes an encryption interface circuit coupled to the encryption circuit. The encryption interface circuit determines first cryptographic parameters based on data in a plaintext input packet and inputs the first cryptographic parameters and plaintext input packet to the encryption circuit. The receive channel includes a decryption interface circuit coupled to the decryption circuit. The decryption interface circuit determines second cryptographic parameters based on data in a ciphertext input packet and inputs the second cryptographic parameters and ciphertext input packet to the decryption circuit.

Abstract: A network interface device has an input configured to receive data from a network. The data is for one of a plurality of different applications. The applications may be supported by a host system. The network interface device is configured to determine which of a plurality of available different caches in a host the data is to be injected. The network interface device will then inject the determined cached with the received data.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for performing a partial reconfiguration of a partially reconfigurable programmable logic device. One of the methods includes providing, to an external memory device storing partial reconfiguration data, a first modified buffer offset. Before receiving partial reconfiguration data at the first modified buffer offset from the external memory, a first portion of prefetched data stored in local buffer memory is written to a configuration space of the partially reconfigurable device. When a first portion of data at the first modified buffer offset is received from the external memory device, the first portion of data at the first modified buffer offset is written to the configuration space of the partially reconfigurable device.

Abstract: Apparatuses and methods generally relating to a sort system, such as may be used in a data processing kernel, for list decoding of a Polar codeword are described. In one such sort system, a sorter circuit is configured to receive and sort path metrics for coded bits of the Polar codeword. The path metrics are obtained from log-likelihood ratios associated with the coded bits. A limiter circuit is configured to cull the sorted path metrics to provide a list having a subset of the path metrics to limit output paths of a list decoder. A normalizer circuit is configured to subtract a path metric of the path metrics or a threshold metric representing a minimum metric respectively from entries in the list to provide normalized path metrics to decode the Polar codeword.

Abstract: A memory circuit is configured for storage of completion queues. Each completion queue can store completion descriptors associated with transfers of data from interrupt source circuits to the memory circuit. A direct memory access circuit provides access to the memory circuit for the interrupt source circuits. An interrupt engine issues interrupt messages for processing the completion descriptors in the completion queues in response to satisfaction of a set of trigger conditions specified in an active interrupt moderation mode. The active interrupt moderation mode is one of multiple available interrupt moderation modes. The interrupt engine bypasses issuing interrupt messages in response to the set of trigger conditions of the active interrupt moderation mode not being satisfied.

Abstract: A memory management unit circuit includes a plurality of ports with a plurality of translation buffer units. Each translation buffer unit includes a translation lookaside buffer circuit and a translation logic circuit configured to perform virtual to physical address translation using the translation lookaside buffer circuit. A translation lookaside buffer circuit prefetch logic circuit monitors virtual memory access requests received at the corresponding port of the memory management unit circuit and detects satisfaction of at least one trigger condition. In response, address translation prefetch requests are generated. A control circuit transmits the address translation prefetch requests to a physical memory circuit and receives address translation data for populating the translation lookaside buffer.

Abstract: Methods and apparatus relate to a 1-to-2 memory interface deserializer circuit that, in a training mode, independently positions even and odd strobes in respective even and odd data windows. In an illustrative example, the deserializer circuit may receive a data signal that encodes even and odd data streams on the rising (even) and falling (odd) edges of a strobe clock signal. During a training mode, the deserializer circuit may independently determine, for example, an optimal temporal delay for each of the even strobe and the odd strobe. Adjustable delay lines dedicated to each of the even and odd strobe signals may simultaneously detect valid data window edges to permit determination of a desired delay to optimally position the strobe signals. Various embodiments may advantageously reduce jitter associated with asymmetric strobe and/or data signals to achieve a predetermined specification (e.g., timing margins) within the corresponding data windows.

Abstract: Examples of the present disclosure provide example devices that include an integrated circuit that has debugging capability. In some examples, a device includes an integrated circuit die. The integrated circuit die includes an input/output (IO) base cell and a debug port. The IO base cell has an interface node and a feedback node. The interface node is configured to be coupled to memory, such as via an interposer, for communication therebetween. The IO base cell is configurable to selectively output to the feedback node a signal that is on the interface node. The debug port has an input node and an output node. The input node is electrically connected to the feedback node. The debug port is configurable to selectively output to the output node a signal that is on the input node. The output node is configured to be coupled to a pin exterior to the integrated circuit die.

Abstract: An example method of configuring a programmable integrated circuit (IC) in a computer system includes: selecting a first region of a programmable fabric of the programmable IC for implementation of a shell circuit, the shell circuit configured to interface with a bus of the computer system; selecting a second region of the programmable fabric for implementation of an application circuit, the application circuit configured to interface with the shell circuit; providing a fence region disposed between the first region and the second region, the fence region including a set of un-configured tiles of the programmable fabric; generating configuration data for a circuit design having the first region, the second region, and the fence region; and loading the configuration data to the programmable IC.

Abstract: A network interface device is provided in a first device. The network interface device comprises an interface configured to receive a first input from a network. The network interface device also has at least one processor configured to provide an output in dependence on contents of the first input and provenance information which uniquely identifies the network interface device, the output being output via the interface to the network.

Abstract: Method and system generally relating to integrated circuits are disclosed. In such a method, a secure lockdown mode for the integrated circuit is initiated. System states of a system internal to the integrated circuit are obtained after initiation of the secure lockdown mode. This obtaining of the system states includes: reading out of the system states from storage devices internal to the integrated circuit; and loading the system states into temporary storage of the integrated circuit. The system states are output via a port of the integrated circuit before closing the port responsive to the secure lockdown mode.