Patents Assigned to Xilinx, Inc.
-
Patent number: 10628547Abstract: Routing a circuit design for implementation in an integrated circuit having a programmable network on chip can include determining Quality of Service (QOS) parameters for data flows of a circuit design, wherein the data flows involve transfers of data between masters and slaves through the programmable network on chip and generating, using a processor, an expression having a plurality of variables representing the data flows, routing constraints, and the QOS parameters. A routing solution can be determined using the processor for the data flows of the circuit design by initiating execution of a SAT solver using the expression.Type: GrantFiled: June 30, 2017Date of Patent: April 21, 2020Assignee: XILINX, INC.Inventors: Ian A. Swarbrick, Dinesh D. Gaitonde, Henri Fraisse
-
Patent number: 10629512Abstract: A method and apparatus are provided that includes an integrated circuit die having an in-chip heat sink, along with an electronic device and a chip package having the same, and methods for fabricating the same. In one example, an integrated circuit die has an in-chip heat sink that separates a high heat generating integrated circuit from another integrated circuit disposed within the die. The in-chip heat sink provides a highly conductive heat transfer path from interior portions of the die to at least one exposed die surface.Type: GrantFiled: June 29, 2018Date of Patent: April 21, 2020Assignee: XILINX, INC.Inventors: Hong-Tsz Pan, Jonathan Chang, Nui Chong, Henley Liu, Gamal Refai-Ahmed, Suresh Ramalingam
-
Patent number: 10628622Abstract: An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array includes obtaining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC, adding at least one first-in-first-out (FIFO) buffer to at least one of the communication channels, and generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.Type: GrantFiled: May 10, 2019Date of Patent: April 21, 2020Assignee: XILINX, INC.Inventors: Mukund Sivaraman, Shail Aditya Gupta, Abnikant Singh
-
Patent number: 10628065Abstract: Some examples of the present disclosure generally relate to integrated circuits that include hardware logic for detecting an edge of a signal. In some examples, an integrated circuit includes a traffic generator, a memory communication path, a comparator, and edge detection hardware logic. The traffic generator, comparator, and edge detection hardware logic are configurable based on a calibration stage. The traffic generator is operable to generate commands to memory via a memory communication path. The comparator is operable to compare data from the memory communication path with known data and to responsively output a comparison status. The data from the memory communication path is in response to the commands generated by the traffic generator. The edge detection hardware logic is operable to detect an edge of a signal based on the comparison status.Type: GrantFiled: June 11, 2018Date of Patent: April 21, 2020Assignee: XILINX, INC.Inventors: Amit Vyas, Ramakrishna R. Gaddam
-
Patent number: 10630301Abstract: A voltage-controlled oscillator (VCO) includes an inductor-capacitor (LC) tank circuit, tuning circuitry, and a plurality of first varactors. The LC tank circuit is configured to produce an oscillating signal and is operable in a plurality of frequency bands. The tuning circuitry is configured to tune the LC tank circuit to operate in a first frequency band of the plurality of frequency bands based at least in part on a temperature of the VCO. The plurality of first varactors are coupled to the LC tank circuit for tuning the oscillating signal to a target frequency within the first frequency band based on a control voltage.Type: GrantFiled: November 15, 2018Date of Patent: April 21, 2020Assignee: Xilinx, Inc.Inventors: Adebabay M. Bekele, Parag Upadhyaya, Didem Z. Turker Melek
-
Patent number: 10621067Abstract: An execution circuit is configured to input data units, perform unit operations on the data units, and register results of the unit operations in response to oscillations of a clock signal. A control circuit controls activation and deactivation of the unit operations. A debug circuit inputs, in parallel with input of the data units to the execution circuit, at least one of the data unit or one or more attributes associated with the data unit. The debug circuit evaluates, upon each input of the at least one of the data unit or the one or more attributes, a breakpoint condition based on the at least one of the data unit or the one or more attributes while the clock signal oscillates. In response to evaluation of the breakpoint condition indicating a break, the debug circuit stops oscillations of the clock signal to the execution circuit.Type: GrantFiled: February 5, 2018Date of Patent: April 14, 2020Assignee: Xilinx, Inc.Inventors: Georgios Tzimpragos, Jason Villarreal, Amitava Majumdar, Kumar Deepak, Yuxiong Zhu
-
Patent number: 10623008Abstract: In an example, a phase-locked loop (PLL) circuit includes an error detector operable to generate an error signal; an oscillator operable to provide an output signal having an output frequency based on the error signal and a frequency band select signal, the output frequency being a frequency multiplier times a reference frequency; a frequency divider operable to divide the output frequency of the output signal to generate a feedback signal based on a divider control signal; a sigma-delta modulator (SDM) operable to generate the divider control signal based on inputs indicative of an integer value and a fractional value of the frequency multiplier, the SDM responsive to an order select signal operable to select an order of the SDM; and a state machine operable to, in an acquisition state, generate the frequency band select signal and set the order of the SDM.Type: GrantFiled: April 30, 2015Date of Patent: April 14, 2020Assignee: XILINX, INC.Inventors: Parag Upadhyaya, Adebabay M. Bekele, Didem Z. Turker Melek, Zhaoyin D. Wu
-
Patent number: 10622951Abstract: Described examples provide for digital communication circuits and systems that implement digital pre-distortion (DPD). In an example, a circuit includes a baseband DPD circuit, up-conversion circuitry, and feedback circuitry. The baseband DPD circuit comprises a baseband signal path and pre-distortion path. The pre-distortion path is configured to generate a pre-distortion signal based on the baseband signal. The baseband DPD circuit includes a first adder configured to add the baseband signal from the baseband signal path and the pre-distortion signal from the pre-distortion path to generate a pre-distorted baseband signal. The up-conversion circuitry is configured to convert the pre-distorted baseband signal to a radio frequency signal. The up-conversion circuitry is configured to be coupled to an input of a cable television (CATV) amplifier.Type: GrantFiled: October 3, 2018Date of Patent: April 14, 2020Assignee: XILINX, INC.Inventors: Xiaohan Chen, Christopher H. Dick, Hongzhi Zhao, Hemang M. Parekh
-
Patent number: 10621299Abstract: Providing dynamic platform support for a programmable integrated circuit (IC) can include loading a circuit design for a programmable IC, wherein the circuit design specifies a link region coupled to a first infrastructure region by first connections, and a kernel region coupled to the first infrastructure region by second connections and generating a base platform from the circuit design by removing the first infrastructure region, the kernel region, and the second connections from the circuit design and adding a wrapper that includes the first connections. A new platform can be generated from the base platform where the new platform includes the link region and, within the wrapper, a second infrastructure region coupled to the link region by the first connections.Type: GrantFiled: February 5, 2018Date of Patent: April 14, 2020Assignee: XILINX, INC.Inventors: Hao Yu, Raymond Kong, Brian Martin, Jun Liu, Kevin Beazley
-
Patent number: 10621132Abstract: Embodiments herein describe techniques for assigning address ranges to ports in switches forming a packet protocol switch network in an integrated circuit. Instead of relying on a designer to provide the addresses, the integrated circuit can include an address bus which is incremented as addresses are assigned to the ports. In one embodiment, the port addresses are assigned from a root device and defines the address range of each branch port and the address of each endpoint in the network. As the address bus reaches an endpoint, an adder in the endpoint increments the value of the address bus (e.g., the current address). The address bus may use serial or parallel data communication to assign the addresses. In another embodiment, instead of using a separate address bus, a data bus typically used for packet communication assigns the addresses to the ports in the network.Type: GrantFiled: May 5, 2017Date of Patent: April 14, 2020Assignee: XILINX, INC.Inventors: Rafael C. Camarota, Ian A. Swarbrick, Kin Yip Sit
-
Patent number: 10623174Abstract: Electrical circuits and associated methods relate to performing a phase alignment by providing N copies of clock alignment circuits, enabling and selecting different clock alignment circuits to achieve an initial phase alignment. In an illustrative example, a phase alignment circuit may include a first clock alignment circuit configured to find a first phase alignment point and a second clock alignment circuit configured to find a second phase alignment point. A control circuit may be configured to select a primary clock alignment circuit from the first clock alignment circuit and the second clock alignment circuit and generate a digital command signal to control a phase interpolator. In various embodiments, by setting the control circuit, the same phase alignment circuit may be used to perform phase alignments between clock domains with different frequencies.Type: GrantFiled: December 12, 2018Date of Patent: April 14, 2020Assignee: XILINX, INC.Inventors: Riyas Noorudeen Remla, Warren E. Cory, Chee Chong Chan
-
Patent number: 10623222Abstract: Techniques related to a data processing engine for an integrated circuit (IC) are described. In an example, a method is provided for vectorized peak detection. The method includes dividing a set of data samples of a data signal, corresponding to a peak detection window (PDW), into a plurality of subsets of data samples each comprising a number of data samples. The method includes performing vector operations on each of the plurality of subsets of data samples. The method includes determining a running index of a sample with a maximum amplitude over the PDW based on the vector operations.Type: GrantFiled: August 30, 2018Date of Patent: April 14, 2020Assignee: XILINX, INC.Inventors: Kaushik Barman, Parag Dighe, Baris Ozgul, Sneha Bhalchandra Date
-
Patent number: 10621129Abstract: A peripheral interconnect for configuring slave endpoint circuits, such as may be in a configurable network, in a system-on-chip (SoC) is described herein. In an example, an apparatus includes a processing system on a chip, a circuit block on the chip, and a configurable network on the chip. The processing system and the circuit block are connected to the configurable network. The configurable network includes a peripheral interconnect. The peripheral interconnect includes a root node and a plurality of switches. The root node and the plurality of switches are connected in a tree topology. First branches of the tree topology are connected to respective slave endpoint circuits of the configurable network. The slave endpoint circuits of the configurable network are programmable to configure the configurable network.Type: GrantFiled: March 27, 2018Date of Patent: April 14, 2020Assignee: XILINX, INC.Inventors: Ian A. Swarbrick, David P. Schultz
-
Patent number: 10620644Abstract: A thermal management system includes an integrated circuit (IC). The IC includes a plurality of digitally addressable sectors. Each sector includes an on-die sensing element. The on-die sensing element includes an on-die temperature sensor configured to measure a sector temperature and provide an analog signal associated with the sector temperature; and an on-die digitizer configured to generate a digital sensed temperature signal based on the analog signal. The IC further includes a first output configured to output a plurality of digital sensed temperature signals from the plurality of sectors.Type: GrantFiled: May 1, 2018Date of Patent: April 14, 2020Assignee: XILINX, INC.Inventors: Suresh P. Parameswaran, Boon Y. Ang, Sarayanan Balakrishnan
-
Patent number: 10614191Abstract: Method and system relate generally to generating a physical design for a circuit design. In such a method, a logical network is obtained from a logical netlist for the circuit design. A physical network for an integrated circuit chip is obtained. The physical network is converted into a routing graph. The logical network and the routing graph are combined to build an extended network. Routing is performed on the extended network for the logical netlist to perform placement and the routing concurrently to provide the physical design.Type: GrantFiled: May 29, 2018Date of Patent: April 7, 2020Assignee: XILINX, INC.Inventors: Henri Fraisse, Dinesh D. Gaitonde
-
Patent number: 10613137Abstract: Methods and apparatus are described relating to a probe assembly having a probe head securing mechanism that includes a lock ring housing and a lock ring disposed in the lock ring housing. In an example, a probe assembly includes a rigid substrate, a circuit board coupled to the rigid substrate, and a probe head securing mechanism. The probe head securing mechanism includes a lock ring housing and a lock ring disposed within the lock ring housing. The circuit board has a surface. The lock ring housing is coupled to the rigid substrate. The circuit board is disposed between the lock ring housing and the rigid substrate. The lock ring is rotatable relative to the lock ring housing. Rotation of the lock ring is configured to move the lock ring in a direction perpendicular to the surface of the circuit board.Type: GrantFiled: December 1, 2017Date of Patent: April 7, 2020Assignee: XILINX, INC.Inventors: Mohsen H. Mardi, Lik Huay Lim, King Yon Lew, Andy Widjaja
-
Patent number: 10613875Abstract: A system includes a runtime generator implemented in programmable circuitry of an integrated circuit, wherein the runtime generator is parameterizable at runtime of the integrated circuit to perform at least one of detecting a symbol pattern within a data stream or generating pseudo random number binary sequences. The system can include a processor configured to execute program code, wherein the processor is configured to provide first parameterization data to the runtime generator. In response to receiving the first parameterization data from the processor at runtime of the integrated circuit, the runtime generator implements a first automaton circuit configured to perform the at least one of the detecting the symbol pattern or the generating the pseudo random number binary sequences.Type: GrantFiled: April 10, 2018Date of Patent: April 7, 2020Assignee: XILINX, INC.Inventors: Patrick Lysaght, Graham F. Schelle, Parimal Patel, Yun Qu
-
Publication number: 20200106668Abstract: A network interface device comprises a plurality of components configured to process a flow of data one after another. A control component is configured to provide one or more control messages in said flow, said one or more control message being provided to said plurality of components one after another such that a configuration of one or more of said components is changed.Type: ApplicationFiled: September 28, 2018Publication date: April 2, 2020Applicant: Xilinx, Inc.Inventors: Steven Leslie Pope, David James Riddoch
-
Publication number: 20200105642Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate, a cover disposed over the first IC die, and a plurality of extra-die conductive posts disposed between the cover and substrate. The extra-die conductive posts provide a heat transfer path between the cover and substrate that is laterally outward of the first IC die.Type: ApplicationFiled: September 28, 2018Publication date: April 2, 2020Applicant: Xilinx, Inc.Inventors: Jaspreet Singh Gandhi, Gamal Refai-Ahmed, Henley Liu, Myongseob Kim, Tien-Yu Lee, Suresh Ramalingam, Cheang-Whang Chang
-
Publication number: 20200104715Abstract: An example method of implementing a neural network includes selecting a first neural network architecture from a search space and training the neural network having the first neural network architecture to obtain an accuracy and an implementation cost. The implementation cost is based on a programmable device of an inference platform. The method further includes selecting a second neural network architecture from the search space based on the accuracy and the implementation cost, and outputting weights and hyperparameters for the neural network having the second neural network architecture.Type: ApplicationFiled: September 28, 2018Publication date: April 2, 2020Applicant: Xilinx, Inc.Inventors: Kristof Denolf, Nicholas Fraser, Kornelis A. Vissers, Giulio Gambardella
