Abstract: An integrated circuit (IC) includes a first kernel circuit implemented in programmable circuitry, a second kernel circuit implemented in programmable circuitry, and a stream traffic manager circuit coupled to the first kernel circuit and the second kernel circuit. The stream traffic manager circuit is configured to control data streams exchanged between the first kernel circuit and the second kernel circuit.

Abstract: A system includes a host system and an integrated circuit coupled to the host system through a communication interface. The integrated circuit is configured for hardware acceleration. The integrated circuit includes a direct memory access circuit coupled to the communication interface, a kernel circuit, and a stream traffic manager circuit coupled to the direct memory access circuit and the kernel circuit. The stream traffic manager circuit is configured to control data streams exchanged between the host system and the kernel circuit.

Abstract: Examples described herein provide for an electronic device apparatus with multiple thermally conductive paths for heat dissipation. In an example, an electronic device apparatus includes a package comprising a die attached to a package substrate. The electronic device apparatus further includes a ring stiffener disposed around the die and on the package substrate, a heat sink disposed on the package, and a wedge disposed between the heat sink and the ring stiffener.

Abstract: Systems and methods for calibrating a ring modulator are described. A system may include a controller configured to provide a first test signal to the ring modulator, determine a first candidate temperature control signal for a heater of the ring modulator when the first test signal is provided to the ring modulator, determine a first optical swing of an optical signal at a drop port of the ring modulator, determine a second candidate temperature control signal for the heater when the first test signal is provided to the ring modulator, determine a second optical swing of an optical signal at the drop port, select an optimal optical swing from the first optical swing and the second optical swing, and select one of the first candidate temperature control signal or the second candidate temperature control signal based on the optimal optical swing selected.

Abstract: A device includes a platform implemented in programmable circuitry of the device. The platform is configured to communicate with a host data processing system. The device includes a first partial reconfiguration region implemented in the programmable circuitry and coupled to the platform. The first partial reconfiguration region is reserved for implementing user-specified circuitry. The device includes timing insulation circuitry implemented in the programmable circuitry and configured to isolate timing of signals passing between the platform and the first partial reconfiguration region.

Abstract: A method of transmitting data for use at a data processing system and network interface device, the data processing system being coupled to a network by the network interface device, the method comprising: forming a message template in accordance with a predetermined set of network protocols, the message template including at least in part one or more protocol headers; forming an application layer message in one or more parts; updating the message template with the parts of the application layer message; processing the message template in accordance with the predetermined set of network protocols so as to complete the protocol headers; and causing the network interface device to transmit the completed message over the network.

Abstract: A network interface device having a hardware module comprising a plurality of processing units. Each of the plurality of processing units is associated with its own at least one predefined operation. At a compile time, the hardware module is configured by arranging at least some of the plurality of processing units to perform their respective at least one operation with respect to a data packet in a certain order so as to perform a function with respect to that data packet. A compiler is provide to assign different processing stages to each processing unit. A controller is provided to switch between different processing circuitry on the fly so that one processing circuitry may be used whilst another is being compiled.

Abstract: A test system for testing a wafer for integrated circuit devices is described. The test system comprises a first plurality of test probes adapted to make electrical contacts to first corresponding contacts of a wafer tested by the test system; a second plurality of test probes adapted to make electrical contacts to second corresponding contacts on a perimeter region of a portion of the wafer tested by the test system; and a control circuit coupled to the first plurality of test probes and the second plurality of test probes; wherein the control circuit determines whether the second plurality of test probes has a proper contact with the wafer based upon signals received by the second plurality of test probes. A method of testing a wafer for an integrated circuit is also described.

Abstract: A circuit arrangement includes an encryption circuit and a decryption circuit. A cryptographic shell circuit has a transmit channel and a receive channel in parallel with the transmit channel. The transmit channel includes an encryption interface circuit coupled to the encryption circuit. The encryption interface circuit determines first cryptographic parameters based on data in a plaintext input packet and inputs the first cryptographic parameters and plaintext input packet to the encryption circuit. The receive channel includes a decryption interface circuit coupled to the decryption circuit. The decryption interface circuit determines second cryptographic parameters based on data in a ciphertext input packet and inputs the second cryptographic parameters and ciphertext input packet to the decryption circuit.

Abstract: A decoder circuit can include low-density parity-check (LDPC) decoder circuitry having a plurality of stages and an LDPC repository configured to store parity-check information associated with one or more LDPC codes. The LDPC repository is configured to determine a stall requirement for a layer of a first data block and perform a memory check for a second data block. The LDPC repository, in response to the stall requirement indicating a stall for the layer of the first data block and determining that the memory check is satisfied, is further configured to schedule processing of the first data block and the second data block in the LDPC decoder circuitry using the parity-check information by interleaving the layer of the first data block and a layer of the second data block through the plurality of stages of the LDPC decoder circuitry.

Abstract: A circuit for determining data error spacing in a data transmitter is disclosed. The circuit comprises a counter; encoding logic configured to receive an output of the counter, wherein the encoding circuit enables generating error spacing information; and a storage element configured to receive an output of the encoding logic.

Abstract: Register pull-out for sequential circuit blocks may include determining, using computer hardware, a net of a circuit design having a driver that is a macro circuit block driving a plurality of loads and determining, using the computer hardware, a placement difficulty of the net based upon a type of the driver and number and type of the plurality of loads. In response to determining that the placement difficulty of the net exceeds a threshold placement difficulty, the computer hardware is capable of modifying the circuit design by pulling a register from the driver to a location on a device external to the driver and changing internal logic of the driver based upon the pulled register.

Abstract: A waveform simulation system with a waveform database architecture satisfies different requirements of different waveform simulation tools. The waveform simulation system includes a waveform database configured to store one or more mappings that map one or more design objects to one or more memory addresses. The waveform simulation system also includes a packet processing module configured to receive simulation data from a simulation tool. The packet processing module is configured to translate the simulation data into translated simulation data that is independent of implementation details of the one or more design objects, based at least in part on the one or more mappings. In some cases, the translated simulation data may include event data stored in the waveform database.

Abstract: A system includes a hardware offload circuit and a slave processor coupled to the hardware offload circuit. The system also includes a processor coupled to the slave processor and configured to execute productivity language instructions. The processor, in response to executing the productivity language instructions, is configured to generate commands and provide the commands to the slave processor. The slave processor, in executing the commands, is configured to monitor operation of the hardware offload circuit and control operation of the hardware offload circuit.

Abstract: FinFET, P-N junctions and methods for forming the same are described herein. In one example, a FinFET is described that includes a fin having a channel region wrapped by a gate, the channel region connecting a source and a drain. A first isolation layer is disposed on a first side of the fin and a second isolation layer is disposed on a second side of the fin, where the second side is opposite of the first side. The second isolation layer has a thickness greater than a thickness of the first isolation layer.

Abstract: Monitoring method and a monitoring device of a deep learning processor, which can effectively monitor running of the deep learning processor, capture an abnormal status in an arbitrary working state, and make the deep learning processor return to a normal state in time is presented. The monitoring method comprises: initializing standard data and storing a standard calculation result corresponding to the standard data, sending the standard data to the deep learning processor, receiving a calculation result returned by the deep learning processor, comparing the received calculation result with the stored standard calculation result, and judging the state of the deep learning processor in accordance with the result of the comparison, judging that the state of the deep learning processor is normal when the compared results are consistent, and judging that the deep learning processor is abnormal when the compared results are inconsistent.

Abstract: Apparatus and associated methods relate to a consolidated power-on-reset system (PORS) at a system-on-chip (SoC) level. In an illustrative example, an integrated circuit may include a first power domain and a second power region. A level shifter circuit may be coupled to translate data from the first power domain to the second power domain. A PORS including a voltage detection circuit, a glitch filter circuit, and logic gates may be configured to generate isolation signals between the first power domain and the second power domain. The level shifter circuit may be enabled in response to the generated isolation signals. By using the isolation signals, multiple power domains on IC may be managed comprehensively during power-up to avoid unstable operation.

Abstract: Event tracing for a system-on-chip (SOC) may be implemented by instrumenting, using a computer, a design for the SOC with instrumentation program code that, responsive to execution by a processor of the SOC, generates software trace events. The design may be specified in a high level programming language. A circuit design specifying an accelerator circuit for a function of the design may be generated using the computer. The accelerator circuit is configured for implementation within programmable circuitry of the SOC. The circuit design may be instrumented to include trace circuitry using the computer. The trace circuitry may be configured to detect hardware trace events for operation of the accelerator circuit, receive the software trace events, and combine the hardware and software trace events into time synchronized trace data.

Abstract: A device may include a plurality of data processing engines, a subsystem, and an SoC interface block coupled to the plurality of data processing engines and the subsystem. The SoC interface block may be configured to exchange data between the subsystem and the plurality of data processing engines.

Abstract: An integrated circuit having an integrated logic analyzer can include a match circuit including at least one match cell, wherein each match cell is programmable at runtime to detect a signal state from a plurality of signal states for a probed signal. The integrated circuit can include a combine circuit configured to generate a first match signal indicating an occurrence of a first trigger condition based upon the detected signal state of each match cell, a capture and control circuit configured to determining addressing for storing trace data corresponding to the probed signal, and a trace storage memory configured to the store trace data at addresses determined by the capture and control circuit.