Patents Assigned to Xilinx, Inc.
  • ANALOG SWITCH HAVING REDUCED GATE-INDUCED DRAIN LEAKAGE
    Publication number: 20160277019
    Abstract: In an example, an apparatus includes an analog switch having an n-type metal oxide semiconductor (NMOS) circuit in parallel with a p-type metal oxide semiconductor (PMOS) circuit between a switch input and a switch output. The analog switch is responsive to an enable signal that determines switch state thereof. The NMOS circuit includes a switch N-channel transistor coupled to a buffer N-channel transistor, a gate of the switch N-channel transistor coupled to the enable signal and a gate of the buffer N-channel transistor coupled to a modulated N-channel gate voltage. The PMOS circuit including a switch P-channel transistor coupled to a buffer P-channel transistor, a gate of the switch P-channel transistor coupled to a complement of the enable signal and a gate of the buffer P-channel transistor coupled to a modulated P-channel gate voltage.
    Type: Application
    Filed: March 17, 2015
    Publication date: September 22, 2016
    Applicant: Xilinx, Inc.
    Inventors: Ionut C. Cical, John K. Jennings, Chandrika Durbha
  • NOISE-SHAPING CREST FACTOR REDUCTION WITH POLYPHASE TRANSFORMING
    Publication number: 20160277229
    Abstract: Apparatus, system and method relates generally to data communication with noise-shaping crest factor reduction using polyphase transformation. In such a method, a composite signal is received by a delay and a waveform generator. The waveform generator is for noise-shaping crest factor reduction using polyphase transformation. The composite signal is delayed by the delay to provide a delayed composite signal. A waveform is generated by the waveform generator from the composite signal. The waveform is output from the waveform generator having clipping noise with respect to bands of corresponding carriers of the composite signal. The waveform is subtracted from the delayed version of the composite signal for peak-to-amplitude power ratio reduction. A reduced peak version of the delayed version of the composite signal delayed is output from the signal combiner.
    Type: Application
    Filed: March 18, 2015
    Publication date: September 22, 2016
    Applicant: XILINX, INC.
    Inventor: Christopher H. Dick
  • Cache coherency
    Patent number: 9448937
    Abstract: A system is disclosed that includes a memory, a processing sub-system, and a programmable logic sub-system. The processing and programmable logic sub-systems each include a respective circuit configured to access a first set of memory addresses that are shared by the processing and programmable logic sub-systems. Each of the processing and programmable logic sub-systems also include a respective cache circuit, configured to cache the first set of addresses of the first memory, and a respective coherent interface circuit configured to communicate data transactions between the respective cache circuit and the memory. The system also includes a cache coherent interconnect configured to maintain coherency between the first cache circuit and the second cache circuit for the first set of addresses.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: September 20, 2016
    Assignee: XILINX, INC.
    Inventor: Sagheer Ahmad
  • Very low power real time clock
    Patent number: 9450569
    Abstract: A very low power real-time clock is provided. The real-time clock includes a real-time clock core and a real-time clock controller, both included in an electronic device. The core is powered both when the electronic device is powered on and when it is powered off. When the electronic device is powered off, the core operates on battery power. The controller is powered off when the electronic device is powered off, to save power. The core maintains a tick count and a seconds count. Because the core is powered on even when the electronic device is powered off, the core continues to update the tick count and seconds count even when the electronic device is powered off. The controller provides access, to external components, to the core. By not powering the controller when the electronic device is powered off, non-core functions do not draw power from a battery.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: September 20, 2016
    Assignee: XILINX, INC.
    Inventor: Ahmad R. Ansari
  • Extracting system architecture in high level synthesis
    Patent number: 9449131
    Abstract: Extracting a system architecture in high level synthesis includes determining a first function of a high level programming language description and a second function contained within a control flow construct of the high level programming description. The second function is determined to be a data consuming function of the first function. Within a circuit design, a port including a local memory is automatically generated. The port couples a first circuit block implementation of the first function to a second circuit block implementation of the second function within the circuit design.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: September 20, 2016
    Assignee: XILINX, INC.
    Inventors: Guoling Han, Stephen A. Neuendorffer
  • Defense against attacks on ring oscillator-based physically unclonable functions
    Patent number: 9444618
    Abstract: Circuits and methods are disclosed for defending against attacks on ring oscillator-based physically unclonable functions (RO PUFs). A control circuit that is coupled to the RO PUF is configured to detect out-of-tolerance operation of the RO PUF. In response to detecting out-of-tolerance operation of the RO PUF, the control circuit disables the RO PUF, and in response to detecting in-tolerance operation, the control circuit enables the RO PUF.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: September 13, 2016
    Assignee: XILINX, INC.
    Inventors: Stephen M. Trimberger, Austin H Lesea
  • Method and apparatus for adaptively tuning an integrated circuit
    Patent number: 9444497
    Abstract: A method and apparatus for adaptively tuning an integrated circuit are disclosed. For example, an integrated circuit (IC) comprises a monitored path comprising circuit elements operating on a clock signal, where a last circuit element of the circuit elements comprises a first flip flop. The IC also comprises a second flip flop operating on an early clock signal, where the early clock signal is phase shifted from the clock signal, and where the second flip flop is coupled to the monitored path prior to the last circuit element. The IC also comprises a transition detection module for detecting when an output from the first flip flop toggles, and an error prediction module to detect a potential error on the monitored path. The IC comprises a controller that is configured to scale a voltage or a frequency of the IC.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: September 13, 2016
    Assignee: XILINX, INC.
    Inventors: Sundararajarao Mohan, Tim Tuan
  • CIRCUITS AND METHODS FOR INTER-PROCESSOR COMMUNICATION
    Publication number: 20160259756
    Abstract: Various example implementations are directed to circuits and methods for communicating between disparate processor circuits. According to an example implementation, a circuit arrangement includes a plurality of processor circuits and an inter-processor communication circuit. The inter-processor communication circuit is configured to provide, for each pair of the processor circuits, a respective communication channel between the pair of processor circuits. The inter-processor communication circuit includes a plurality of buffers including a respective first buffer and a respective second buffer for each communication channel. An access control circuit included in the inter-processor communication circuit is configured to restrict write access to the respective first buffer to the first processor circuit and restrict write access to the respective second buffer to the second processor circuit.
    Type: Application
    Filed: March 4, 2015
    Publication date: September 8, 2016
    Applicant: XILINX, INC.
    Inventors: Sagheer Ahmad, Soren Brinkmann
  • Centering baud-rate CDR sampling phase in a receiver
    Patent number: 9438409
    Abstract: In an example, an apparatus for clock data recovery (CDR) includes a data slicer operable to generate data samples derived from a transmitted signal, and an error slicer operable to generate error samples derived from a transmitted signal. The apparatus further includes a CDR circuit operable to generate sampling clock phase for the data slicer and the error slicer from output of the data samples and the error samples. The apparatus further includes a decision adapt circuit operable to set a decision threshold of the error slicer, wherein for each main-cursor data sample of the data samples the decision adapt circuit is operable to adjust the decision threshold based on a function of at least one pre-cursor data sample, at least one post-cursor data sample, or a combination of at least one pre-cursor data sample and at least one post-cursor data sample.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: September 6, 2016
    Assignee: XILINX, INC.
    Inventors: Yu Liao, Geoffrey Zhang
  • Circuit network with an error detection system for mitigation of error propagation
    Patent number: 9436562
    Abstract: An apparatus relating generally to an error detection system is disclosed. The apparatus includes a first data bus and a second data bus. A first circuit is coupled for communication via the first data bus. A plurality of storage elements are coupled to the first data bus and the second data bus. A second circuit is coupled for communication via the second data bus. The error detection system is coupled to the first data bus and the second data bus. The error detection system is coupled to compare first data on the first data bus with corresponding second data on the second data bus. The error detection system is configured to generate an error signal responsive to mismatch between the first data and the second data.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: September 6, 2016
    Assignee: XILINX, INC.
    Inventors: Matthew H. Klein, Chen W. Tseng
  • Hierarchical preset and rule based configuration of a system-on-chip
    Patent number: 9436785
    Abstract: Hierarchical preset and rule base configuration of a system-on-chip (SOC) includes receiving a user input selecting a first circuit block of the SOC for enablement and determining, using a processor, a first top level preset according to the user input for the first circuit block. Selected intermediate presets are determined from a plurality of hierarchically ordered presets for the first circuit block. Low level presets are automatically determined for the first circuit block according to the selected intermediate presets for the first circuit block. The low level presets are output, e.g., by loading them into the SOC.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: September 6, 2016
    Assignee: XILINX, INC.
    Inventors: Somdutt Javre, Pradeep Kumar Mishra, Siddharth Rele
  • Circuits for and methods of controlling power within an integrated circuit
    Patent number: 9438244
    Abstract: A circuit for controlling power within an integrated circuit comprises a plurality of circuit blocks; a global control signal routed within the integrated circuit; and a plurality of power control blocks. Each power control block is coupled to a corresponding circuit block of the plurality of circuit bocks and has a first input coupled to receive a reference voltage and a second input coupled to receive the global control signal. The global control signal enables, for each circuit block, the coupling of the reference voltage to the corresponding circuit block. A method of controlling power within an integrated circuit is also disclosed.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: September 6, 2016
    Assignee: XILINX, INC.
    Inventors: Santosh Kumar Sood, Brian C. Gaide, Steven P. Young
  • Method and circuits for superclocking
    Patent number: 9436786
    Abstract: Methods and circuits for superclocked operation of a plurality of functionally-equivalent logic circuits are disclosed. One of the plurality of functionally-equivalent logic circuits is selected according to a selection algorithm. In response to selecting one of the plurality of functionally-equivalent logic circuits, superclocked operation of the selected one of the plurality of functionally-equivalent logic circuits is enabled. Superclocked operation of other ones of the plurality of functionally-equivalent logic circuits is disabled. The selected one of the plurality of functionally-equivalent logic circuits is used to process a portion of the input data set at the superclocked clock frequency.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: September 6, 2016
    Assignee: XILINX, INC.
    Inventor: John D. Corbett
  • CURRENT-MODE LOGIC CIRCUIT HAVING A WIDE OPERATING RANGE
    Publication number: 20160254813
    Abstract: In one example, a current-mode logic (CML) circuit includes a differential transistor pair having a differential input port configured to receive a differential input voltage, a bias port configured for coupling to a current source, and a differential output port. The CML circuit further includes a load circuit coupled to the differential output port. The load circuit includes an active inductive load, a cross-coupled transistor pair, and a switch coupled between the cross-coupled transistor pair and the differential output.
    Type: Application
    Filed: February 27, 2015
    Publication date: September 1, 2016
    Applicant: Xilinx, Inc.
    Inventor: Junho Cho
  • High-density integrated circuit memory
    Patent number: 9431095
    Abstract: A memory circuit includes an input stage having N input ports and N output ports, wherein N is an integer greater than one. The memory circuit further includes an N:1 port multiplexer coupled to the N output ports of the input stage and configured to time division multiplex the N output ports to one multiplexed port. The memory circuit also includes a random access memory matrix and a 1:N port multiplexer. The memory circuit is coupled to the multiplexed port. The 1:N port multiplexer is coupled to the random access memory matrix and is configured to de-multiplex signals received from the random access memory matrix into N output ports.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: August 30, 2016
    Assignee: XILINX, INC.
    Inventor: Ephrem C. Wu
  • Radio frequency current steering digital to analog converter
    Patent number: 9432036
    Abstract: In one example, a current steering circuit for a digital-to-analog converter (DAC) includes a source-coupled transistor pair responsive to a differential gate voltage; a current source coupled to the source-coupled transistor pair operable to source a bias current; a load circuit coupled to the source-coupled transistor pair operable to provide a differential output voltage; a driver having a first input, a second input, and a differential output, the differential output providing the differential gate voltage; and combinatorial logic having a data input, a clock input, a true output, and a complement output, the true output and the complement output respectively coupled to the first input and the second input of the driver, the combinatorial logic operable to exclusively OR a data signal on the data input and a clock signal on the clock input.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: August 30, 2016
    Assignee: XILINX, INC.
    Inventors: Donnacha Lowney, Christophe Erdmann
  • Dynamic capacitors for tuning of circuits
    Patent number: 9431812
    Abstract: A circuit includes a signal line formed of at least one conductive element and a shield at least partially encompassing the signal line. The circuit further includes a first dynamic capacitor located between the shield and the signal line. The first dynamic capacitor is configured to provide a first variable amount of capacitance.
    Type: Grant
    Filed: September 18, 2012
    Date of Patent: August 30, 2016
    Assignee: XILINX, INC.
    Inventor: John E. McGrath
  • Optical communication circuits
    Patent number: 9432121
    Abstract: Various apparatuses, circuits, systems, and methods for optical communication are disclosed. In some implementations, an apparatus includes a package substrate and f first interposer mounted on the package substrate. The apparatus also includes a logic circuit and an optical interface circuit connected to the logic circuit via the first interposer. One of the optical interface circuit or the logic circuit is mounted on the first interposer. The optical interface circuit includes a driver circuit configured to receive electronic data signals from the logic circuit. The optical interface circuit also includes an optical transmitter circuit coupled to the driver circuit and configured to output optical data signals encoding the electronic data signals.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: August 30, 2016
    Assignee: XILINX, INC.
    Inventors: Austin H. Lesea, Stephen M. Trimberger
  • Out-of-band (OOB) detection circuit for serial/deserializer (SERDES)
    Patent number: 9432007
    Abstract: An out-of-band (OOB) detection circuit includes: a positive input node; a negative input node; a resistive circuit comprising a first resistor coupled between a first supply node and a first node, a variable resistor coupled between the first node and a second node, and a second resistor coupled between the second node and a ground; a first comparator configured to compare a difference between a positive input signal received at the positive input node and a negative input signal received at the negative input node against a positive threshold value, and a second comparator configured to compare the difference between the positive input signal received at the positive input node and the negative input signal received at the negative input node against a negative threshold value.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: August 30, 2016
    Assignee: XILINX, INC.
    Inventors: Jingfeng Gong, Cheng-Hsiang Hsieh
  • Stacked silicon package assembly having enhanced lid adhesion
    Patent number: 9418909
    Abstract: A method and apparatus are provided which improve the adhesion of a lid to an IC die of an IC (chip) package. In one embodiment, a chip package assembly is provided that includes an IC die, a package substrate and a lid. The IC die is coupled to the package substrate. The lid has a first surface and a second surface. The second surface of the lid faces away from the first surface and towards the IC die. The second surface of the lid has a plurality of engineered features. The adhesive couples the plurality of engineered features of the lid to the IC die.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: August 16, 2016
    Assignee: XILINX, INC.
    Inventors: Raghunandan Chaware, Inderjit Singh