Abstract: In one example, a current steering circuit includes an output transistor pair responsive to a first gate bias voltage. The current steering circuit further includes a first switch comprising a first source-coupled transistor pair coupled to the output transistor pair and responsive to a first differential gate voltage, and a second switch comprising a second source-coupled transistor pair coupled to the output transistor pair and responsive to a second differential gate voltage. The current steering circuit further includes a current source configured to source a bias current. The current steering circuit further includes a third switch comprising a third source-coupled transistor pair coupled between the current source and each of the first switch and the second switch, the third source-coupled transistor pair responsive to a third differential gate voltage.

Abstract: An apparatus includes a plurality of programmable hardware resources and an analog-to-digital converter (ADC) disposed on an IC die. The ADC is configured to quantize values of one or more analog parameters of the IC die. The apparatus also includes a configuration control circuit configured to program the programmable hardware resources in response to a set of configuration data. The programmable hardware resources are programmed to implement a set of circuits specified by the configuration data and to connect the ADC to respective nodes of the IC die for sampling the analog parameters. The apparatus also includes an interface circuit coupled to the ADC and configured to generate a control signal based on quantized values of the one or more analog parameters from the ADC. The interface circuit outputs the control signal to a power supply coupled to a power terminal of the IC die.

Abstract: An apparatus for calibrating a three-dimensional thermography fault isolation tool, includes: a substrate having two or more pins; a first semiconductor die coupled to the substrate; a first heat generating test component at the first semiconductor die; and a second heat generating test component, wherein the first heat generating test component and the second heat generating test component are located at different respective heights; wherein the first heat generating test component is configured to produce a first temperature change in response to a voltage applied by the three-dimensional thermography fault isolation tool to the two or more pins; and wherein the second heat generating test component is configured to produce a second temperature change in response to the voltage or another voltage applied by the three-dimensional thermography fault isolation tool.

Abstract: In one example, a semiconductor assembly comprises a first IC die, a second IC die, and a bridge module. The first IC die includes, on a top side thereof, first interconnects of a plurality of interconnects and first inter-die contacts of a plurality of inter-die contacts. The second IC die includes, on a top side thereof, second interconnects of the plurality of interconnects and second inter-die contacts of the plurality of inter-die contracts. The bridge module is disposed between the first interconnects and the second interconnects and includes bridge interconnects on a top side thereof, the bridge interconnects mechanically and electrically coupled to the plurality of inter-die contacts, and layer(s) of conductive interconnect disposed on the top side thereof to route signals between the first IC and the second IC. A back side of the bridge module does not extend beyond a height of the plurality of interconnects.

Abstract: A LDPC decoder utilizes a new schedule that breaks a dependency between data of different layers of a parity check matrix, so that the forward scan in the next layer can begin to perform after a predetermined time has elapsed (i.e. a delay) since the backwards scan of the previous layer has begun, and before the backwards scan of the previous layer is completed. Accordingly, the computation at the next layer can begin as soon as possible.

Abstract: In an example, an apparatus for CDR includes at least one data register, at least one edge register having an input coupled to an output of the at least one data register, and a phase detector having inputs coupled to the output of the at least one data register and an output of the at least one edge register. The apparatus further includes a frequency accumulator coupled to an output of the phase detector, a dynamic gain circuit coupled to the output of the phase detector, and a phase accumulator and code generator circuit configured to generate codes to control a phase interpolator based on an output of the dynamic gain circuit and an output of the frequency accumulator.

Abstract: A signed multiplier circuit includes a two-dimensional array of substantially similar logic blocks. Each of the logic blocks is programmable to implement any of four multiply functions of first and second inputs, in which: the first and second inputs are both signed; the first and second inputs are both unsigned; the first input is signed and the second input is unsigned; and the first input is unsigned and the second input is signed. Each logic block includes rows and columns of sub-circuits, e.g., logical AND gates and full adders. One row and one column of each logic block include a programmably invertible AND gate, with the row and column being independently controlled. The ability to program the logic block to perform all four of these functions enables the combination of rows and columns of the logic blocks to build large signed multipliers of virtually any size.

Abstract: A computer-implemented method of caching data in a managed runtime computing environment can include loading source data and comparing content of the source data with at least one of a plurality of cache entries. Each cache entry can include a representation of previously received source data and a transformation of the previously received source data. A transformation for the source data from a cache entry can be selected or a transformation for the source data can be generated according to the comparison. The transformation for the source data can be output.

Abstract: An integrated circuit includes a die having a conductive layer. The conductive layer includes a data wire, a first power supply wire of a first voltage potential, and a second power supply wire of a second voltage potential different from the first voltage potential. A segment of the data wire is located between, and substantially parallel to, a segment of the first power supply wire and a segment of the second power supply wire. Further, the first power supply wire is coupled to a first probe structure; and, the second power supply wire is coupled to a second probe structure.

Abstract: In some disclosed implementations, a system-on-chip on a first IC die includes a boot loader circuit configured to search a first boot device, of a plurality of boot devices coupled to and external to the first IC die, for an uncorrupt boot image. The boot loader circuit is configured to search a second boot device of the plurality of boot devices for an uncorrupt boot image, in response to failing to find an uncorrupt boot image in the first boot device. The boot loader is also configured to load a set of instructions included in the uncorrupt boot image into a memory circuit of the SOC, in response to finding an uncorrupt boot image.

Abstract: An apparatus relating generally to a system-on-chip is disclosed. In this apparatus, the system-on-chip has at least one analog block, an input/output interface, a data test block, and a processing unit. The processing unit is coupled to the input/output interface to control access to the at least one analog block. The data test block is coupled to the at least one analog block through the input/output interface. The processing unit is coupled to the data test block and configured to execute test code having at least one test pattern. The data test block under control of the test code executed by the processing unit is configured to test the at least one analog block with the test pattern.

Abstract: An inductor for an integrated circuit can include a first turn comprising a first through silicon via (TSV) coupled to a second TSV. The inductor can include a third TSV coupled to the second TSV.

Abstract: Determining delays of paths in a circuit design includes determining whether or not each path of the plurality of paths matches a path definition of a plurality of path definitions in a path database. For each path that matches a path definition, a first path delay value associated with the matching path definition is read from the path database and associated with the matching path of the circuit design. For each path that does not match any of the path definitions, respective element delay values of elements of the path are read from an element database. A second path delay value of the non-matching path is computed as a function of the respective element delay values, and the second path delay value is associated with the path. The first and second path delay values are output along with information indicating the associated paths.

Abstract: In an example implementation, a level-shifter circuit in an integrated circuit (IC) includes a plurality field-effect transistors (FETs) coupled to provide: a first inverter having an input port configured to receive an input signal having a first supply voltage, an output port, and a bias port; a second inverter having an input port coupled to the output port of the first inverter, an output port, and a bias port coupled to a second supply voltage; a diode-connected FET coupled between the second supply voltage and the bias port of the first inverter; a first FET in parallel with the diode-connected FET having a gate coupled to the output of the second inverter; and a second FET in parallel with the diode-connected FET and the first FET having a gate configured to receive a mode select signal.

Abstract: A device for controlling a power-on reset signal can include a constant current source, for controlling a reference current that is independent of a supply voltage, and a trip point detector circuit driven by the reference current. The trip point detector circuit detects when the supply voltage of the device exceeds a first trip point voltage, and de-asserts the power-on reset signal when the supply voltage exceeds the first trip point voltage. The first trip point voltage can be controlled by a sum of a threshold voltage of a first n-type metal-oxide-semiconductor transistor, a voltage drop across a first resistor, and a threshold voltage of a first p-type metal-oxide-semiconductor transistor. The device may further include a hysteresis circuit, for detecting when the supply voltage falls below a second trip point voltage and causing the trip point detector circuit to reassert the power-on reset signal.

Abstract: A circuit for controlling the operation of a memory system having different types of memory is described. The circuit comprises a first memory having a first type of memory element and having a first access time; a second memory having a second type of memory element and having a second access time, wherein the second type of memory element is different than the first type of memory element; a memory control circuit enabling access to the first memory and the second memory; a delay buffer coupled to the second memory to compensate for a difference in the first access time and the second access time; and a circuit for merging outputs of the first memory and delayed outputs of the second memory to generate ordered output data. A method of controlling the operation of a memory system is also disclosed.

Abstract: In an example, a programmable integrated circuit (IC) includes programmable logic, a processing system, and a network controller. The network controller includes a media access control unit (MAC), a first interface to a physical transceiver, a second interface to the processing system, and a third interface between the MAC and the programmable logic.

Abstract: An apparatus relates generally to providing a divided signal output. In such an apparatus, a controller is coupled to receive a reference frequency count and a feedback frequency count to determine a difference therebetween to provide a control setting. A divider is coupled to receive the control setting to provide the divided signal output. The divider includes an adjustable load impedance. The control setting is coupled to adjust the load impedance of the divider to adjust a self-resonance frequency of the divider.

Abstract: A method for providing charge protection to a die during formation of an integrated circuit, includes bonding the die to an interposer to form an unprotected stacked silicon component; encapsulating the unprotected stacked silicon component with a mold compound to cover at least a top surface of the die; grinding the mold compound to reduce a thickness of the mold compound; bonding a carrier wafer to the mold compound; removing the carrier wafer from the mold compound; and removing the mold compound from the top surface of the die after the carrier wafer is removed from the mold compound, to expose the top surface of the die.

Abstract: An inverter includes: a PMOS comprising: a p-type source region, a p-type drain region, a p-channel region between the p-type source region and the p-type drain region, and a PMOS metal gate region; a NMOS, comprising: an n-type source region, an n-type drain region, an n-channel region between the n-type source region and the n-type drain region, and a NMOS metal gate region; an insulating layer above the p-channel region and the n-channel region, wherein the PMOS metal gate region and the NMOS metal gate region are above the insulating layer; and a gate contact between the NMOS metal gate region and the PMOS metal gate region.