Abstract: A method for asynchronous time multiplexing of information with synchronous interfacing includes, responsive to a first edge of a clock signal, asynchronously loading first data, including first multiple sets of data for multiple operations, into a first asynchronous shift register. The first data is asynchronously unloaded from the first asynchronous shift register to a function block for processing to provide second data, including second multiple sets of data as results of the multiple operations. The second data is asynchronously loaded into a second asynchronous shift register. Responsive to a second edge of the clock signal, the second data is asynchronously unloaded from the second asynchronous shift register as the results of the multiple operations. The first edge and the second edge of the clock signal are associated with a same period of the clock signal.

Abstract: An approach for management of memory in a programmable integrated circuit (IC) includes configuring a memory map of the programmable IC with an association of a first subset of addresses of memory address space of the programmable IC and physical memory of the programmable IC. The memory map is further configured with an association of a second subset of addresses of the memory address space and a virtual memory block. At least a portion of a cache memory of the programmable IC is locked to the second subset of addresses.

Abstract: A method for determining or configuring supply voltage and threshold voltage for a design implementation of a given electronic design, includes: determining a first set of supply voltage-threshold voltage combinations that meet timing requirements for the design implementation; performing power analysis using a processor; and selecting a supply voltage-threshold voltage combination from the first set of supply voltage-threshold voltage combinations based at least in part on a result from the power analysis, wherein the selected supply voltage-threshold voltage combination provides an optimal amount of power consumption for the design implementation.

Abstract: Devices and methods for performing a cyclic redundancy check are disclosed. For example, a device has a splitter for splitting a data word into a plurality of paths. The device also has a plurality of cyclic redundancy check units. Each of the units is for processing a respective one of the paths. In addition, each of the units includes a first output port for outputting a cyclic redundancy check value for a packet ending within the unit and a second output port for outputting a cyclic redundancy check value for a packet starting or ongoing within the unit.

Abstract: A user interface is provided for selection of a previously specified scenario from a plurality of previously specified scenarios. Each previously specified scenario includes a previously specified topology of the electronic system, one or more previously specified parameter values applied to the electronic system, a previously specified traffic profile, and respective precompiled values of one or more measurands. In response to user selection of one of the previously specified scenarios, the precompiled values of the measurands are displayed. The user interface further provides for specification of a scenario. In response to user specification of a scenario, traffic emulation circuitry in the programmable IC is configured to execute the scenario. The value of the at least one measurand is computed and displayed.

Abstract: A circuit for realigning data received at a receiver is disclosed. The circuit comprises a plurality of memory arrays; a plurality of multiplexers, wherein each multiplexer is coupled to select an address for data to be output by a memory array of the plurality of memory arrays; an output multiplexer coupled to select the outputs of the plurality of memory arrays; and a memory control circuit coupled to the plurality of multiplexers and the output multiplexer, the memory control circuit coupling select signals to the plurality of multiplexers and the output multiplexer to enable generating realigned data. A method of realigning data received at a receiver is also disclosed.

Abstract: An integrated circuit (IC) can include an analog region of a die of the IC. The analog region includes analog circuitry. The IC further includes a plurality of solder bumps implemented on a surface of the die in an area in vertical alignment with the analog region of the die.

Abstract: An apparatus includes a plurality of programmable hardware resources and an analog-to-digital converter (ADC) disposed on an IC die. The ADC is configured to quantize values of one or more analog parameters of the IC die. The apparatus also includes a configuration control circuit configured to program the programmable hardware resources in response to a set of configuration data. The programmable hardware resources are programmed to implement a set of circuits specified by the configuration data and to connect the ADC to respective nodes of the IC die for sampling the analog parameters. The apparatus also includes an interface circuit coupled to the ADC and configured to generate a control signal based on quantized values of the one or more analog parameters from the ADC. The interface circuit outputs the control signal to a power supply coupled to a power terminal of the IC die.

Abstract: In an example, a control device includes a data path, a clock path, a multiplexing circuit, and a calibration unit. The data path comprises a data delay unit coupled to a data input of a sampling circuit. The clock path comprises a clock delay unit coupled to a clock input of the sampling circuit. The multiplexing circuit selectively couples a reference clock or a data bus to an input of the data delay unit, and selectively couples the reference clock or a source clock to an input of the clock delay unit. The calibration unit is coupled to a data output of the sampling circuit. The calibration unit is operable to adjust delay values of the data delay unit and the clock delay unit based on the data output of the sampling circuit to establish and maintain a relative delay between the data path and the clock path.

Abstract: An embodiment of an apparatus to reduce supply voltage noise with capacitors of an interposer of a stacked die is disclosed. In this embodiment, an interposer is coupled to a first integrated circuit die using a first plurality of interconnects. A substrate is coupled to the interposer using a second plurality of interconnects. The substrate includes a supply voltage plane and a ground plane, each of which is coupled to the first integrated circuit die using the second plurality of interconnects, the interposer, and the first plurality of interconnects. The interposer includes capacitors coupled in parallel using the supply voltage plane, the ground plane, and the second plurality of interconnects, where capacitance from capacitors of the interposer is provided to the first integrated circuit die using the supply voltage plane and the ground plane of the substrate.

Abstract: A circuit for providing voltage level shifting in an integrated circuit includes an inverter having an input coupled to receive an input signal having a first voltage level; an output stage having a first transistor coupled in series with a second transistor, and an output node between the first transistor and the second transistor generating an output signal having a second voltage level. A gate of the second transistor is coupled to an output of the inverter. A pull-up transistor is coupled between a reference voltage having the second voltage level and a gate of the first transistor. A switch is coupled between the gate of the first transistor and the gate of the second transistor to control a voltage at the gate of the first transistor. A method of providing voltage level shifting in an integrated circuit is also disclosed.

Abstract: A system for digital pre-distortion includes: a transmitter configured to transmit at least one transmission data signal; a receiver configured to receive at least one receive data signal and to receive the at least one transmission data signal; and at least one amplifier, associated with the transmitter, configured to receive at least one pre-distortion control signal sent from the receiver; wherein the at least one pre-distortion control signal is related to the at least one transmission data signal.

Abstract: In an example, an apparatus for signal classification in a digital pre-distortion (DPD) system includes a positive frequency path including a first half-band low pass filter (LPF) operable to filter samples of an input digital samples after positive frequency translation; a negative frequency path including a second half-band LPF operable to filter the samples of the input digital samples after negative frequency translation; a power estimation circuit coupled to the positive frequency path and the negative frequency path, the power estimation circuit operable to determine a first average power based on output of the first half-band LPF, a second average power based on output of the second half-band LPF, and a total average power of the input digital samples; and a controller operable to determine a frequency content metric from the first average power and the second average power, and to select a set of filter coefficients for the DPD system based on the frequency content metric and the total average power.

Abstract: A method includes initiating a boot of a system-on-chip coupled to a boot device. The boot is initiated from boot code stored in nonvolatile memory responsive to a power-on-reset. Under control of the boot code: a first register value is loaded into a register; a name string from the boot code is accessed; the first register value is obtained from the register; and the first register value and name string are converted to a first string value, which is provided as a first filename. The boot device is searched for a boot image file with the first filename. If the first filename is not found in the boot device, the first register value is incremented to provide a second register value. The obtaining, converting, and searching are repeated using a second filename generated using the second register value, and a valid filename for the boot image file is iteratively generated.

Abstract: An integrated circuit structure can include an interposer having a plurality of conductive layers and a die coupled to the interposer through an internal interconnect structure. The integrated circuit structure can include an inductor implemented within at least one of the conductive layers of the interposer. The inductor can include a first terminal and a second terminal. The first terminal and the second terminal can be coupled to the internal interconnect structure.

Abstract: Clock region partitioning and clock routing includes creating partitions for a plurality of clocks of a circuit design, and legalizing the partitions using a processor according to a number of clocks in each partition and assignment of clock distribution tracks. Roots for implementing clock trees of the clocks are selected within the partitions.

Abstract: A data interface enabling the calibration of input data comprises a first data receiver having a first plurality of input data lines coupled to receive a corresponding first plurality of data bits associated with a data bus, the first data receiver having a first control circuit enabling calibration of the first plurality of input data lines; and a second data receiver having a second plurality of input data lines coupled to receive a corresponding second plurality of data bits associated with the data bus, the second data receiver having a second control circuit enabling calibration of the second plurality of data lines. The first plurality of input data lines of the first data receiver are calibrated in parallel with the second plurality of input data lines of the second data receiver.

Abstract: In a method relating generally to starting a plurality of transmitters, a sequence is initiated for each of the plurality of transmitters having corresponding data buffers. Latency is set for each of the data buffers responsive to execution of the sequence. The sequence includes: obtaining a read address associated with a read clock signal; obtaining a write address associated with a write clock signal; determining a difference between the read address and the write address; asserting a flag signal associated with the difference; and adjusting the read clock signal to change the difference to locate a change of state location for the flag signal to set the latency for a data buffer of the data buffers.

Abstract: In an example, a memory control device includes an output circuit, an output delay unit, and a write-levelization controller. The output circuit is coupled to provide an output signal comprising a data signal or data strobe signal for a synchronous dynamic random access memory (SDRAM) system having a plurality of ranks. The output delay unit is coupled to apply an output delay to a bitstream to be transmitted to generate the output signal. The output delay includes an aggregate of a de-skew delay and a write-levelization delay. The write-levelization delay controller is coupled to adjust the write-levelization delay for each write transaction to the SDRAM system of a plurality of write transactions based on a selected rank of the plurality of ranks. The de-skew delay is the same across the plurality of ranks for each of the plurality of write transactions.

Abstract: A circuit for controlling power within an integrated circuit comprises a plurality of circuit blocks; a global control signal routed within the integrated circuit; and a plurality of power control blocks. Each power control block is coupled to a corresponding circuit block of the plurality of circuit bocks and has a first input coupled to receive a reference voltage and a second input coupled to receive the global control signal. The global control signal enables, for each circuit block, the coupling of the reference voltage to the corresponding circuit block. A method of controlling power within an integrated circuit is also disclosed.