Patents Assigned to Xilinx, Inc.
  • Capacitor structure in an integrated circuit
    Patent number: 9524964
    Abstract: In an example, a capacitor in an integrated circuit (IC), includes: a first finger capacitor formed in at least one layer of the IC having a first bus and a second bus; a second finger capacitor formed in the at least one layer of the IC having a first bus and a second bus, where a longitudinal edge of the second bus of the second finger capacitor is adjacent a longitudinal edge of the first bus of the first finger capacitor and separated by a dielectric gap; and a first metal segment formed on a first layer above the at least one layer, the first metal segment being electrically coupled to the first bus of the first finger capacitor and increasing a width and a height of the first bus of the first finger capacitor.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: December 20, 2016
    Assignee: XILINX, INC.
    Inventors: Jing Jing, Shuxian Wu
  • Adaptive multiple-input multiple-output (MIMO) data detection and precoding
    Patent number: 9525470
    Abstract: A system includes a memory and an integrated circuit coupled to the memory. The integrated circuit is configured to communicate data in a channel characterized as a space having at least a frequency dimension. Anchor locations within the space correspond to respective regions of the space. The integrated circuit is further configured to determine a first inverse of a first matrix that corresponds to a first channel matrix for a first anchor location of the anchor locations. The first anchor location corresponds to a first region of the regions. The integrated circuit is further configured to perform an access link process for a second location other than the first anchor location but within the first region, the access link process using the first inverse determined for the first anchor location.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: December 20, 2016
    Assignee: XILINX, INC.
    Inventors: Michael Wu, Christopher H. Dick, Christoph E. Studer
  • Optical communication circuits
    Patent number: 9520949
    Abstract: Various apparatuses, circuits, systems, and methods for optical communication are disclosed. In some implementations an optical transmitter includes an optical data port configured to engage an optical fiber. The optical transmitter also includes a plurality of lasers coupled to the optical data port and configured and arranged to transmit respective optical signals over the optical fiber via the optical data port when selected. A control circuit of the optical transmitter is configured to receive an input data signal and encode the input data signal for transmission over the optical fiber by selecting one or more of the plurality of lasers at a time. The control circuit is configured to select one or more of the plurality of lasers at a time according to one of a frequency modulation encoding algorithm or an amplitude modulation encoding algorithm.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: December 13, 2016
    Assignee: XILINX, INC.
    Inventors: Stephen M. Trimberger, Austin H. Lesea
  • Method of and device for processing data using a pipeline of processing blocks
    Patent number: 9519486
    Abstract: A method of processing data in an integrated circuit is described. The method comprises establishing a pipeline of processing blocks, wherein each processing block has a different function; coupling a data packet having data and meta-data to an input of the pipeline of processing blocks; and processing the data of the data packet using predetermined processing blocks based upon the meta-data. A device for processing data in an integrated circuit is also described.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: December 13, 2016
    Assignee: XILINX, INC.
    Inventors: Michaela Blott, Thomas B. English, Kornelis A. Vissers
  • CHANNEL ADAPTIVE ADC-BASED RECEIVER
    Publication number: 20160352557
    Abstract: A receiver relates generally to channel adaptation. In this receiver, a first signal processing block is coupled to a communications channel. The first signal processing block includes: an AGC block and a CTLE block for receiving a modulated signal for providing an analog signal; an ADC for converting the analog signal to digital samples; and an FFE block for equalizing the digital samples to provide equalized samples. A second signal processing block includes: a DFE block for receiving the equalized sampled for providing re-equalized samples; and a slicer coupled to the DFE block for slicing the re-equalized samples. A receiver adaptation block is coupled to the first signal processing block and the second signal processing block. The receiver adaptation block is configured for providing an AGC adaptation, a CTLE adaptation, and a slicer adaptation to the communications channel.
    Type: Application
    Filed: May 27, 2015
    Publication date: December 1, 2016
    Applicant: Xilinx, Inc.
    Inventors: Yu Liao, Geoffrey Zhang, Hongtao Zhang, Kun-Yung Chang, Toan Pham, Zhaoyin D. Wu
  • Methods for flip chip stacking
    Patent number: 9508563
    Abstract: A method for flip chip stacking includes forming a cavity wafer comprising a plurality of cavities and a pair of corner guides, placing a through-silicon-via (TSV) interposer with solder bumps coupled to a surface of the TSV interposer on the cavity wafer, such that the solder bumps are situated in the plurality of cavities and the TSV interposer is situated between the pair of corner guides, placing an integrated circuit (IC) die on another surface of the TSV interposer, such that the IC die, the TSV interposer, and the solder bumps form a stacked interposer unit, removing the stacked interposer unit from the cavity wafer, and bonding the solder bumps of the stacked interposer unit to an organic substrate such that the stacked interposer unit and the organic substrate form a flip chip.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: November 29, 2016
    Assignee: XILINX, INC.
    Inventors: Woon-Seong Kwon, Suresh Ramalingam
  • Latency control in a transmitter/receiver buffer
    Patent number: 9509640
    Abstract: In a method for buffering, a buffer buffers data responsive to read and write clock signals. A flag signal from the buffer is for a fill level thereof. The flag signal is toggled responsive to the data buffered being either above or below a set point for the fill level. A phase of the write clock signal is adjusted to a phase of the read clock signal responsive to the toggling of the flag signal. The write clock signal is used to control latency of the buffer. The adjusting of the phase of the write clock signal includes: generating an override signal responsive to the toggling of the flag signal; and inputting the read clock signal and the override signal to a phase adjuster to controllably adjust the phase of the write clock signal to the phase of the read clock signal during operation.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: November 29, 2016
    Assignee: XILINX, INC.
    Inventors: David F. Taylor, Matthew H. Klein, Vincent Vendramini
  • Interconnect multiplexers and methods of reducing contention currents in an interconnect multiplexer
    Patent number: 9509307
    Abstract: An interconnect multiplexer comprises a plurality of CMOS pass gates of a first multiplexer stage coupled to receive data to be output by the interconnect multiplexer; an output inverter coupled to the outputs of the plurality of CMOS pass gates, wherein an output of the output inverter is an output of the interconnect multiplexer; and a plurality of memory elements coupled to the plurality of CMOS pass gates; wherein inputs to the plurality of CMOS pass gates are pulled to a common potential during a startup mode. A method of reducing contention currents in an integrated circuit is also disclosed.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: November 29, 2016
    Assignee: XILINX, INC.
    Inventors: Vikram Santurkar, Anil Kumar Kandala, Santosh Yachareni, Shidong Zhou, Robert Fu, Philip Costello, Sandeep Vundavalli, Steven P. Young, Brian C. Gaide
  • TRANSMITTER CONFIGURED FOR TEST SIGNAL INJECTION TO TEST AC-COUPLED INTERCONNECT
    Publication number: 20160341780
    Abstract: In one example, a driver circuit includes a differential transistor pair configured to be biased by a current source and including a differential input and a differential output. The driver circuit further includes a resistor pair coupled between a node pair and the differential output, a transistor pair coupled between a voltage supply and the node pair, and a bridge transistor coupled between the node pair. The driver circuit further includes a pair of three-state circuit elements having a respective pair of input ports, a respective pair of control ports, and a respective pair of output ports. The pair of output ports is respectively coupled to the node pair. The pair of control ports is coupled to a common node comprising each gate of the transistor pair and a gate of the bridge transistor.
    Type: Application
    Filed: May 20, 2015
    Publication date: November 24, 2016
    Applicant: XILINX, INC.
    Inventors: Scott D. McLeod, Hsung Jai Im, Stanley Y. Chen
  • Relaxation oscillator
    Patent number: 9503058
    Abstract: Various example implementations are directed to circuits and methods for generating a clock signal. According to an example embodiment, a circuit arrangement includes a relaxation oscillator configured to output a clock signal. The clock signal has an oscillation frequency dependent on a reference current provided to the relaxation oscillator, an operating temperature of the relaxation oscillator, and a supply voltage used to power the relaxation oscillator. The circuit arrangement also includes a current source coupled to the relaxation oscillator and configured to generate the reference current. The current source is configured to adjust the reference current, in response to a change in one or more of the temperature of the relaxation oscillator and the supply voltage, to inhibit change in the oscillation frequency of the clock signal.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: November 22, 2016
    Assignee: XILINX, INC.
    Inventors: Ionut C. Cical, John K. Jennings, Edward Cullen
  • Circuits for and methods of testing the operation of an input/output port
    Patent number: 9500700
    Abstract: An integrated circuit enabling the communication of data is described. The integrated circuit comprises an input/output port; a plurality of data converter circuits; and programmable interconnect circuits coupled between the input/output port and the plurality of data converter circuits, the programmable interconnect circuits enabling a connection of the plurality of data converter circuits to the input/output port of the integrated circuit. A method of enabling the communication of data in an integrated circuit is also described.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: November 22, 2016
    Assignee: XILINX, INC.
    Inventors: Xiaobao Wang, Burton M. Leary, Amitava Majumdar, Arvind R. Bomdica
  • Virtualization of programmable integrated circuits
    Patent number: 9503093
    Abstract: A programmable IC includes a plurality of programmable resources, a plurality of shareable logic circuits coupled to the plurality of programmable resources, and a virtualization circuit. The plurality of programmable resources includes programmable logic circuits and programmable routing resources. The virtualization circuit is configured to manage sharing of the plurality of shareable logic circuits between a plurality of user designs implemented in the plurality of programmable resources. The user designs are communicatively isolated from one another on the programmable IC.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: November 22, 2016
    Assignee: XILINX, INC.
    Inventors: Kimon Karras, Michaela Blott, Kornelis A. Vissers
  • Circuit for and method of implementing a time-interleaved analog-to-digital converter
    Patent number: 9503115
    Abstract: A circuit for implementing a time-interleaved analog-to-digital converter is described. The circuit comprises a sampling clock generator configured to receive a reference clock signal having a first frequency.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: November 22, 2016
    Assignee: XILINX, INC.
    Inventors: Jaewook Shin, Hiva Hedayati
  • Testing critical paths of a circuit design
    Patent number: 9501604
    Abstract: A method of testing a circuit design includes generating, for each net of each critical path in the circuit design, a respective ring oscillator circuit design. The ring oscillator circuit design has a source gate coupled to a destination gate via the net and a feedback path that couples an output pin of the destination gate to an input pin of the source gate. Configuration data are generated to implement a respective ring oscillator circuit from each ring oscillator circuit design, and a programmable integrated circuit is configured with the configuration data. The method determines a delay of the net of each ring oscillator circuit.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: November 22, 2016
    Assignee: XILINX, INC.
    Inventors: Geetesh More, Srinivasan Dasasathyan, Nagaraj Savithri
  • Noise-shaping crest factor reduction with polyphase transforming
    Patent number: 9503301
    Abstract: Apparatus, system and method relates generally to data communication with noise-shaping crest factor reduction using polyphase transformation. In such a method, a composite signal is received by a delay and a waveform generator. The waveform generator is for noise-shaping crest factor reduction using polyphase transformation. The composite signal is delayed by the delay to provide a delayed composite signal. A waveform is generated by the waveform generator from the composite signal. The waveform is output from the waveform generator having clipping noise with respect to bands of corresponding carriers of the composite signal. The waveform is subtracted from the delayed version of the composite signal for peak-to-amplitude power ratio reduction. A reduced peak version of the delayed version of the composite signal delayed is output from the signal combiner.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: November 22, 2016
    Assignee: XILINX, INC.
    Inventor: Christopher H. Dick
  • User-configurable error handling
    Patent number: 9495239
    Abstract: A method for operating a programmable IC is disclosed. A set of circuits specified by a set of configuration data is operated in a set of programmable resources. In response to one of a set of status signals indicating an error, a value indicative of an error is stored in a respective one of a plurality of error status registers. The values stored in the plurality of error status registers are provided to an error handling circuit included in the set of circuits specified by the set of configuration data and operated in the programmable resources. At least one error handling process is performed by the error handling circuit as a function of values stored in the plurality of error status registers.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: November 15, 2016
    Assignee: XILINX, INC.
    Inventors: Sagheer Ahmad, Bradley L. Taylor, Ahmad R. Ansari, Tomai Knopp
  • Clock domain boundary crossing using an asynchronous buffer
    Patent number: 9497050
    Abstract: An apparatus includes a plurality of channels, where each of the channels includes an asynchronous buffer, a latency determination block, a tap selection circuit, and a variable delay. A latency locator is configured to identify a longest latency from among the channels and is coupled to provide the longest latency to the tap selection circuit of each of the channels. For each of the channels: the latency determination block is coupled to the asynchronous buffer to determine a latency value for the asynchronous buffer; the tap selection circuit is coupled to receive the latency value and the longest latency; the tap selection circuit is coupled to the variable delay; and the tap selection circuit is configured to select a tap of taps of the variable delay responsive to the latency value and the longest latency.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: November 15, 2016
    Assignee: XILINX, INC.
    Inventor: Julian M. Kain
  • Programmable power reduction technique using transistor threshold drops
    Patent number: 9496871
    Abstract: An integrated circuit includes: a voltage rail; voltage control circuitry coupled to the voltage rail; and a circuit block coupled to the voltage control circuitry; wherein the voltage control circuitry is selectively configurable to operate the circuit block in at least a first mode of operation and a second mode of operation; wherein in the first mode of operation, the circuit block receives a voltage that is substantially the same as a voltage of the voltage rail; and wherein in the second mode of operation, the circuit block receives a voltage that is less than the voltage of the voltage rail by a threshold voltage.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: November 15, 2016
    Assignee: XILINX, INC.
    Inventors: Benjamin S. Devlin, Brian C. Gaide, Santosh Kumar Sood
  • Virtualization of memory for programmable logic
    Patent number: 9495302
    Abstract: A processing sub-system is configured to execute a program using a set of virtual memory addresses to reference memory locations for storage of variables of the program. A programmable logic sub-system is configured to implement a set of I/O circuits specified in a configuration data stream, each of the I/O circuits having a respective ID and configured to access one of the variables. A memory management circuit is configured to map the virtual memory addresses to physical memory addresses of a memory and map IDs to the physical address used to store the corresponding variables. A TLB is configured to receive a memory access request, from the I/O circuits, each request indicating an ID and provide, to the memory, a memory access request indicating the physical memory address that is mapped to the ID.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: November 15, 2016
    Assignee: XILINX, INC.
    Inventor: Sagheer Ahmad
  • Analog-to-digital converter circuit and method of implementing an analog-to-digital converter circuit
    Patent number: 9490832
    Abstract: An analog-to-digital converter circuit is described.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: November 8, 2016
    Assignee: XILINX, INC.
    Inventors: Lei Zhou, Hiva Hedayati