Abstract: A timing source is provided for sending timing information via a packet network. The source comprises a clock for generating the timing information and a packet-forming section for forming a sequence of packets for transporting the timing information to a destination node. A time-stamping section inserts into each packet of the sequence a transmission time derived from the clock and acts as an output section for forwarding the packets to the network at the respective transmission times. In one mode, the packet forming section forms all of the packets of the sequence with the largest size which the packet network is capable of transporting. In another mode, the packets of the sequence have a distribution of sizes which may be fixed or which may vary in response to traffic conditions.

Abstract: A method of synchronising first and second clocks coupled respectively to ingress and egress interfaces 6,7 of a packet network 1, the method comprising calculating a minimum packet Transit Time over the network 1 in each of successive time intervals, and varying the frequency of the second clock so as to track variations in the minimum packet Transit Time.

Abstract: A power supply comprises transistors whose conduction paths are connected in series and whose control terminals receive a reference voltage. The common terminal at one end of the series-connected conduction paths provides a regulator output whereas output terminals of the transistors are connected to charge storage capacitors, which are charged by respective power generators for scavenging energy from the environment. The transistors begin conducting in sequence so that the storage capacitors begin contributing sequentially to the output current as each transistor conducts in sequence. The capacitors are charged up when they are not contributing to the output current.

Abstract: A method for distributing timing information across a packet network includes generating timing signals at a master clock at predictable intervals using a clock reference of a given frequency. The timing signals are broadcast or multicast to a plurality of slave clocks over the packet network, preserving the timing signal intervals. At each slave clock, the intervals between successively received timing signals are determined. A clock recovery algorithm is applied to the determined intervals to recover in substantially real time the original clock frequency. The local clock frequency of the slave clock is synchronized to the recovered frequency.

Abstract: Apparatus and method for transmitting and reproducing stereophonic audio signals are disclosed. The method comprises splitting first and second channels into two frequency bands, combining the lower frequency band signals of the two channels, and transmitting the combined signals of the two channels or signals representative thereof. The apparatus comprises: a splitter for splitting each of the two channels into two frequency bands, a combiner, for combining the lower frequency band signals of the two channels, and a transmitter for transmitting the combined signals, or signals representative thereof, and the higher frequency band signals of the two channels, or signals representative thereof.

Abstract: A method of recovering a clock signal for a TDM output from packets of TDM data which have been transmitted over a packet network, from a source having a source TDM clock to a destination having a destination TDM clock. The method includes providing at least some packets with a Remote Time stamp representing the state of the source TDM clock when the packet is created; providing said at least some packets with a Local Timestamp representing the state of the destination TDM clock when the packet is received; determining a Transit Time value representing the difference between said Local and Remote Timestamps; and controlling the clock frequency of the TDM output on the basis of said Transit Time as determined above.

Abstract: A time division multiplex switching apparatus is provided for switching channels from any number of input data streams, each of which may have any of a plurality of data rates, to any of a plurality of output data streams, each of which may likewise have any one of a plurality of data rates. An input block 1 comprises a respective input channel for each input stream. Each channel has a variable delay circuit. The outputs of the channels are supplied to a buffer memory 3 which stores data from the input channels in a first order and reads out the data in a second order according to the channel connections required. A controller 2 controls the variable delay circuits 12–14 independently of each other so as to align the data streams from the input channels irrespective of the input stream data rates. For example, the streams may be aligned such that the zeroth channel of a predetermined frame in the input streams appear consecutively at the outputs of the input channels.

Abstract: An integrated circuit device includes an amplifier stage comprising a pair of transistors (134A, 134B), the respective bases or gates of which are connected together, as well as the respective emitters or sources. The respective drains or collectors of the transistors are capacitively coupled (166) so as to be effectively shorted at the frequencies of operation of the amplifier, A biasing circuit arrangement (144) is also provided which employs bias control feedback to set the bias currents for the transistors. The biasing circuit arrangement takes as its input the current flowing at one of the electrodes (160) of one of the transistors.

Abstract: A single conversion tuner is provided for receiving digital terrestrial broadcast signals. The tuner comprises a single frequency changer comprising a mixer and local oscillator controlled by a PLL synthesiser. A non-alignable variable low pass filter is provided between the tuner input and the mixer, which is of the image reject type. The bandwidth of the filter is varied so as to track the local oscillator frequency to provide sufficient attenuation of the image channel without requiring any alignment during manufacture.

Abstract: An electrical component structure (14) comprises a plurality of overlying substantially parallel layers (15, 16). Each layer (15, 16) provides a lattice (17, 20) comprising a first set of conductive tracks arranged substantially orthogonal to, and electrically connected with, a second set of conductive tracks. Conductive islands (18, 22) are located in windows of the lattices (17, 20), the conductive islands being electrically isolated from the tracks. The lattice (17, 20) of each layer (15, 16) is electrically connected to the conductive islands (22, 18) of the other adjacent layer (16, 15).

Abstract: A method of providing data for transmission on a time division multiplexed (TDM) serial data stream. The method comprises mapping channels of the TDM stream to contexts, each context comprising a set of memory buffers for storing data to be transmitted. Data is extracted from the contexts in a sequence defined by said mapping and transmitting the extracted data on the TDM stream. When a buffer or buffers of a context become empty, a buffer refill request is generated to cause data to be read from a memory to refill the buffer, wherein each buffer refill request is assigned a priority. The context buffers are refilled in an order defined by the respective priorities of the refill requests.

Abstract: A Ternary/Content Addressable Memory (T/CAM) design is presented. The CAM includes a rule table implemented using a Random Access Module (RAM) storing n rule entries. An n-to-1 multiplexer module, responsive to a value C of a cycle counter, varying between 0 to n-1, provides a selected C'th rule entry to a comparator block which performs a comparison between the selected C'th rule entry and a matching key. The resulting comparison result together with the value C are used to decode the matched rule. In implementing a TCAM, a bitmask table implemented using a RAM module storing n bitmask entries is used. An n-to-1 multiplexer module, responsive to the value C provides a corresponding C'th bitmask to a masking module which modifies the comparison result to ignore a subgroup of results of bitwise comparisons between the C'th rule entry and the matching key.

Abstract: A mixer circuit arrangement 30 comprises a complementary transconductor circuit 31 and a mixer stage 32. The complementary transconductor circuit 31 includes two paths in parallel between a positive supply voltage VDD and ground G and is connected directly between the voltage supply terminals VDD and G. The first path includes a P-type MOS transistor TP1 and an N-type MOS transistor TN1 connected in series. Similarly, the second path includes a P-type MOS transistor TP2 and an N-type MOS transistor TN2 connected in series. The gate electrodes of the P-type transistors TP1 and TP2 are connected to a voltage bias Vbp via high value bias resistors Rb, and the gate electrodes of the N-type transistors TN1 and TN2 are connected to a second voltage bias Vbn via high value bias resistors Rb. The mixer stage 32 is connected between the output of the complementary transconductor circuit 31 and a load, the load also being connected to one of the supply terminals.

Abstract: A mixer circuit arrangement for frequency-translating a voltage input signal by an amount dependent on the frequency of a local oscillator signal to provide an output signal. The arrangement comprises an input stage 33 and a mixer stage 32, the input stage 33 being arranged to convert the voltage input signal into differential current signals and the mixer stage 32 being arranged to mix the differential current signals with the local oscillator signal to provide the output signal. Means 34,35 is provided for injecting a compensation current into the input stage 33 so as to balance the differential current signals provided to the mixer stage 32.

Abstract: An analogue single conversion tuner comprises a plurality of channels (1, 2, 3) for covering the whole of a desired reception bandwidth. Each tuner comprises an image reject mixer (18) connected to the tuner input (4) by a single tracking filter (16), for example of the single-tuned type.

Abstract: An LNA for use as an input stage of a radio frequency tuner comprises an inverting amplifier stage and a transconductance stage. The amplifier stage has an input connected via an input resistance to an input of the amplifier and via a feedback resistance to an output of the amplifier stage. The transconductance stage passes a current through the input resistance which is substantially proportional to the output voltage of the amplifier stage.

Abstract: A data and clock recovery circuit is provided for generating a recovered version of a transmitted data stream. The data and clock recovery circuit comprises three main circuit modules, namely a data recovery circuit, a clock recovery circuit, and a detector circuit. The data recovery circuit is arranged to receive a data stream, and to generate therefrom an estimate of the signal levels for each bit-period of the originally transmitted data stream. The estimates of the signal levels are stored within the data recovery circuit and are sampled by the clock recovery circuit so that the original data stream is recovered. The data recovery circuit is also arranged to generate a so-called “word metric” which is a quality factor representing the accuracy of the estimated signal levels. The clock recovery circuit is arranged to use both the received data stream, and the word metric generated in the data recovery circuit, to determine whether or not the current sampling time is optimal.

Abstract: A tuner comprises a frequency changer which converts an input signal to a predetermined fixed intermediate frequency. The frequency changer is followed by an IF filter having a filter parameter, such as center frequency, which is electronically adjustable. A controller adjusts the adjustable filter characteristic so as to achieve a predetermined desired filtering performance, such as ensuring that the filter center frequency corresponds to the desired intermediate frequency. The controller comprises a local oscillator having the same type of tuned circuit as the IF filter. A phase locked loop compares the local oscillator frequency with a reference frequency and controls the tuned circuits of the IF filter and the local oscillator.

Abstract: A reticle for use in a photolithography process for exposing a photoresist layer in the production of a component which is formed from a plurality of adjacent exposed areas. The reticle includes an exposure aperture adapted to allow light to pass through the reticle, a patterned area within the exposure aperture which defines at least part of the functional design of the component, and one or more “stitching” structures located close to one or more of the edges of the exposure aperture. The “stitching” structures are arranged to create “stitching” marks on the photoresist, which can be used to determine whether the adjacent exposed areas have been accurately positioned.

Abstract: A tuner comprises a first frequency changer with a mixer and local oscillator. The output of the frequency changer is connected to a first intermediate frequency filter, whose output is connected to a second frequency changer. The output of the frequency changer is connected to the usual second intermediate frequency filter and to an amplitude detector. A reference oscillator is connectable under control of a controller via a multiplexer to the input of the mixer. During an alignment mode of the tuner, the reference signal from the oscillator is supplied to the mixer and the local oscillators and are controlled by the controller to sweep across a frequency range encompassing all possible pass frequencies of the filter. The controller monitors the output of the detector so as to establish the frequency response of the filter. Frequency offsets are then stored in the synthesizers and so as to center each channel during a reception mode on the actual center frequency of the filter.