Abstract: A method is provided for performing photolithography on a substrate which has a first region on a lower level and a second region on an upper level, wherein a first pattern area exists within said first region, a second pattern area exists within said second region, and at least said first and second regions are coated with a photoresist, the method comprising: a) exposing the photoresist through a first mask so as to expose said first region including said first pattern area, and thus create a first pattern in said first pattern area, but not expose said second pattern area; and b) exposing the photoresist through a second mask so as to expose said second pattern area, and thus create a second pattern in said second pattern area, but not expose said first pattern area, and also to expose an area of said first region which lies adjacent said second region.

Abstract: A digital tuner has an input tuning range with lower and upper limit frequencies. An up converter converts an input signal to an intermediate frequency signal whose frequency is higher than the upper frequency limit of the input range. A downconverter is a zero intermediate frequency quadrature converter which converts the intermediate frequency signal to in-phase and quadrature baseband signals. The upconverter has a local oscillator fundamental frequency which is greater than the upper frequency limit of the input tuning range.

Abstract: An integrated circuit capacitor and an integrated circuit are provided. The integrated circuit capacitor includes at least first, second and third conducting plates. The first conducting plate is positioned between the second and third plates. A first dielectric layer is positioned between the first and third conducting plates. A second dielectric layer is positioned between the first and second conducting plates. An “overlap portion” of the second conducting plate extends beyond the edge of the first conducting plate and towards the third conducting plate. The capacitor is arranged so that the electrical breakdown voltage between the overlap portion and the third conducting plate is lower than the electrical breakdown voltage between the first and second conducting plates.

Abstract: An optical router comprises a substantially planar substrate, a stator fixed to and projecting from an upper surface of the substrate, and a rotor surrounding the stator so as to be rotatable about the stator. At least one optical guiding component is formed in or on the rotor. A substantially planar layer is provided on the substrate surrounding the rotor and has a plurality of optical waveguides formed therein, the waveguides opening at least one end onto a space surrounding the rotor. The stator rotor, and planar layer are formed on the substrate by a series of deposition and etching steps such that the rotor may be rotated about the stator so as to align the optical guiding component with one or more of the waveguide openings.

Abstract: A polar loop transmitter circuit arrangement includes a circuit input, a circuit output and a controllable signal source. A modulator is coupled between the signal source and the output, whilst a first logarithmic amplifier is provided having its input coupled to the circuit input. A second logarithmic amplifier is also provided having its output coupled to the circuit output. An output of each logarithmic amplifier is coupled to a respective input of a comparator, and an output of the comparator is coupled to an input of the modulator. The logarithmic amplifiers can be successive detection logarithmic amplifiers, such amplifiers having an RF output which is amplitude limited and can be designed to have constant phase limited output.

Abstract: A single conversion frequency converter comprises an image reject mixer and a local oscillator. The local oscillator comprises a variable frequency oscillator and a variable divider. The variable divider supplies to the mixer a local oscillator signal whose frequency is a sub-multiple of the frequency of the variable frequency oscillator.

Abstract: An arbiter (7) is provided for a QMS having multiple queue users (5A to 5D), each having real time requirements for mastership of a bus (31). The arbiter (7) is arranged so that the amount of time that each queue user (5A to 5D) can gain bus access is a percentage of the total bus time.

Abstract: A zero or near zero IF frequency changer for use in a digital tuner comprises multipliers which receive the RF input signal from an input. The multipliers receive quadrature local oscillator signals from a first oscillator of an arrangement which comprises first and second phase-locked loops. The first phase-locked loop comprises a programmable divider, a comparator and a control loop so that the first oscillator is phase-locked to a second oscillator. A second phase-locked loop comprises the second oscillator and a synthesizer containing a reference oscillator to which the second oscillator is phase-locked. The output frequency of the second oscillator is in a frequency band which is outside the RF input frequency band of the frequency changer.

Abstract: A method is provided of forming a low resistance contact between a poly-silicon resistor of an integrated circuit and a conducting material, the method comprising the steps of: a) covering the resistor with an insulating layer; b) etching at least one contact opening in the insulating layer; c) cleaning the insulating layer to remove any residues from the etching process; d) applying phosphoric acid; and e) depositing a conducting layer which forms an electrical contact with said resistor.

Abstract: A QAM demodulator comprises a timing synchronizer whose output is supplied via an adaptive equalizer to a carrier synchronizer, all of which are controlled by a controller. The timing synchronizer resamples the incoming signal in the digital domain with a sampling period which, during an acquisition mode, sweeps between limit values at different rates. The controller begins an acquisition cycle at the highest rate and monotonically lowers the sweep rate until timing lock is achieved. The sampling rate is then fixed at the correct value. Similarly, the controller sweeps the local oscillator of a phase locked loop in the carrier synchronizer initially at a highest rate and at progressively lower rates until the carrier synchronizer locks to the phase of the incoming signal.

Abstract: A radio frequency amplifier of improved intermodulation performance is provided by connecting first and second transconductance amplifiers in antiphase so that third order intermodulation products cancel each other but the reduction in gain is relatively small. The transconductance stages comprise long tail pairs of transistors provided with tail current sources formed by transistors whose bases are connected to a bias voltage source. The first transistor has an emitter connected via a resistor to ground. The second transistor has an emitter connected via another resistor to the emitter of the first transistor.

Abstract: A polar loop transmitter circuit arrangement includes a circuit input, a circuit output, a controllable signal source, a modulator connected between the signal source and the output, a first amplifier having its input connected to the circuit input, a second amplifier having its input connected to the circuit output, and a comparator. Each amplifier preferably includes respective amplitude detector and signal modifier portions connected in series between their respective inputs and outputs. An output of each of the amplifiers is connected to a respective input of the comparator, and an output of the comparator is connected to a control input of the modulator. The amplifiers may each be characterized by transfer functions that are generally logarithmic. Each amplifier's signal modifier portion may further include an analog-to-digital converter, a digital signal modifier, and a digital-to-analog converter.

Abstract: A method of producing an antifuse, comprises the steps of: depositing a layer of undoped or lightly doped polysilicon on a layer of silicon dioxide on a semiconductor wafer; doping one region of the polysilicon P+; doping another region of the polysilicon N+, leaving an undoped or lightly doped region between the P+ and N+ regions; and forming electrical connections to the P+ and N+ regions.

Abstract: An integrated circuit test structure comprises a potential divider and an array of test circuits. Each test circuit comprises series-connected chains of integrated circuit connections between test voltage lines. Each test circuit also comprises a comparator in the form of a MOSFET having a gate connected to the center point of the chains and a source connected to the output of the potential divider. The drain of the transistor is connected to an input for a bias voltage.

Abstract: A frequency modulation system is disclosed which includes a voltage-controlled oscillator (VCO) 43 and a phase detector 47 configured to receive an output signal from the VCO. The phase detector is arranged to output an error signal representing the phase difference between the signal from the VCO and a reference signal. The system also includes control means 62 arranged to monitor the error signal to derive an indication of the frequency deviation of the VCO, and, in accordance with this derivation, to maintain the frequency deviation of the VCO substantially constant.

Abstract: A signal handling stage provides variable gain, for example for automatic gain control functions, in a radio frequency tuner. The stage comprises a transconductance stage having negative feedback via further transconductance stage. The output current of the transconductance stage is supplied to an AGC core, which steers the output current between output loads and loads for driving the transconductance stage in accordance with an AGC voltage. The amount of negative feedback is therefore varied in accordance with the AGC voltage. For relatively low gain, a large amount of feedback is used and this improves the distortion performance. For relatively high gain, the negative feedback is reduced but a good noise figure can be achieved.

Abstract: A semiconductor device comprises a substrate (11) having an insulating layer (12) formed on a surface thereof, and a silicon layer (13) located on a surface of the insulating layer. A trench (14) extends from a surface of the silicon layer (13) through the insulating layer (12) and into the substrate (11). An insulating liner (14a) is located on the side walls and the base of the trench (14), and an in-fill (14b) of thermally-conductive material is formed within the insulating liner. The insulating liner (14a), the in-fill material (14b) and the distance over which the trench 14) extends into the substrate (11) are such as to promote flow of heat from the silicon layer (13) to the substrate.

Abstract: A device for storing and accessing digital video data comprises first processing means 1 for implementing an operating system and a video system. A hard disk drive 7 is partitioned to provide a video file system storage area and an operating system file system storage area. A Hard Disk Drive Controller 8 controls access to the hard disk drive 7, the Hard Disk Drive Controller 8 comprising at least one register 14 for storing parameters defining a hard disk drive access operation and indicating the status of that operation. Two further registers 12,13 are associated with the video system and the operating system respectively, each further register being arranged to store parameters defining a hard disk drive access operation received from the associated system, and parameters indicating the status of that operation. Second processing means exchanges parameters between the register 14 of the Hard Disk Drive Controller 8 and those of said two further registers 12,13.

Abstract: An integrated circuit having a substrate and an LC tank circuit comprises an inductor with parallel capacitors. The capacitors include triple plate integrated capacitors having a highest metal plate, a common middle plate and a lowest metal plate. The lowest plate is connected to a virtual ground node. A control circuit element connected to the middle plate allows the resonant frequency of the tank circuit to be controlled.

Abstract: A data queue system comprises plural memory blocks defined in memory, and a queue which comprises a number of memory blocks each including a link to the following block in the data queue. A queue descriptor includes identities which identify: the final block in the queue, the memory location where the most recent read commit occurred (and optionally an offset from a predetermined location in that block), the memory location where the most recent write commit occurred (and optionally an offset from a predetermined location in that memory block), the size of the blocks, the memory location the most recent write occurred, the number of unused blocks, the number of blocks which contain data to be read, the type of data queue, the memory location where the most recent read occurred and the number of blocks which have been read since the most recent read commit.