Abstract: A semiconductor device comprises a substrate (11) having an insulating layer (12) formed on a surface thereof, and a silicon layer (13) located on a surface of the insulating layer. A trench (14) extends from a surface of the silicon layer (13) through the insulating layer (12) and into the substrate (11). An insulating liner (14a) is located on the side walls and the base of the trench (14), and an in-fill (14b) of thermally-conductive material is formed within the insulating liner. The insulating liner (14a), the in-fill material (14b) and the distance over which the trench 14) extends into the substrate (11) are such as to promote flow of heat from the silicon layer (13) to the substrate.

Abstract: A method of fabricating a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device with an elevated source 29 and drain 30. A MOSFET region is defined on the surface of a silicon substrate 18, and a central area of that region removed by etching down to a predefined depth. Raised areas 29,30 on either side of the resulting recess 25 are doped to form the drain and a source, such that an active channel of the MOSFET device is provided wholly beneath the base of the recess 25.

Abstract: A tuner demodulator alignment system adjusts the centre-frequency of the PLL-demodulator VCO to achieve alignment with the center-frequency of the IF entering the demodulator by: injecting into the PLL stage a signal having a frequency equal to the nominal center-frequency of the IF, electronically adjusting, e.g. by means of a digital-to-analogue converter (DAC) controlled from a tuner micro-controller, the VCO frequency until this frequency is aligned with the injection frequency, then removing the injection signal and reverting to normal tuner operation. Alignment with the injection frequency may be signalled by a change in logical stage of an AFC flag signal provided by the PLL stage and employed during normal use of the tuner. This may be repeated on an ad-hoc basis, e.g. whenever channels are changed by the user, or more periodically by the tuner software, or may be performed on a one-off basis only on the production bench.

Abstract: A polar loop transmitter circuit arrangement comprises a circuit input, a circuit output, a controllable signal source, a modulator connected between the signal source and the circuit output, a first signal-amplitude-sensitive element having its input connected to the circuit input, a second signal-amplitude-sensitive element having its input connected to the circuit output, a comparator, and at least one controllable attenuator. An output of each of the signal-amplitude-sensitive elements is connected to a respective input of the comparator, and an output of the comparator is connected to a control input of the modulator. Another controllable attenuator may also be connected between the circuit output and an input of the second signal-amplitude-sensitive element. The signal-amplitude-sensitive elements may correspond to amplitude detectors in some embodiments of the technology, and to logarithmic amplifiers in other embodiments.

Abstract: A controllable attenuator has an input and an output, and comprises a first resistive element, a first capacitor connected in series between the input and the output, a first controllable shunting transistor connected between the output and a supply terminal via a second resistive element, and a controllable bypass transistor connected between the input and the output. The controllable attenuator may form part of a radio receiver circuit, the attenuator being positioned between a matching circuit and a low-noise amplifier.

Abstract: A polar loop transmitter circuit arrangement includes a circuit input, a circuit output, a controllable signal source, a modulator connected between the signal source and the output, a first amplifier having its input connected to the circuit input, a second amplifier having its input connected to the circuit output, and a comparator. Each amplifier preferably includes respective amplitude detector and signal modifier portions connected in series between their respective inputs and outputs. An output of each of the amplifiers is connected to a respective input of the comparator, and an output of the comparator is connected to a control input of the modulator. The amplifiers may each be characterized by transfer functions that are generally logarithmic. Each amplifier's signal modifier portion may further include an analog-to-digital converter, a digital signal modifier, and a digital-to-analog converter.

Abstract: A radio frequency amplifier includes first and second transconductance stages 20, 21, the product of whose transconductances is negative. The input and output of the first stage form the input and output of the amplifier. The output of the first stage is provided with a load 22 whereas the output of the second stage 21 is provided with a load 23 and is fed back to the input of the first stage.

Abstract: A frequency doubler circuit arrangement comprises a full wave rectifier circuit having an input and a first terminal, the first terminal being connected to a first supply terminal via a first current source, and the input forming an input of the frequency doubler circuit arrangement. A biased transistor circuit is also provided, having a first terminal connected to the first supply terminal via a second current source and being connected to the first terminal of the rectifier circuit. Output terminals of the rectifier circuit and the biased transistor circuit form differential output terminals of the frequency doubler circuit arrangement. The respective outputs of the rectifier circuit and the biased transistor circuit may be connected to a second supply terminal via either an active filter load or a passive filter load, such as an inductance-capacitance-resistance filter.

Abstract: A mixer circuit arrangement 30 comprises a complementary transconductor circuit 31 and a mixer stage 32. The complementary transconductor circuit 31 includes two paths in parallel between a positive supply voltage VDD and ground G and is connected directly between the voltage supply terminals VDD and G. The first path includes a P-type MOS transistor TP1 and an N-type MOS transistor TN1 connected in series. Similarly, the second path includes a P-type MOS transistor TP2 and an N-type MOS transistor TN2 connected in series. The gate electrodes of the P-type transistors TP1 and TP2 are connected to a voltage bias Vbp via high value bias resistors Rb, and the gate electrodes of the N-type transistors TN1 and TN2 are connected to a second voltage bias Vbn via high value bias resistors Rb. The mixer stage 32 is connected between the output of the complementary transconductor circuit 31 and a load, the load also being connected to one of the supply terminals.

Abstract: A polar loop transmitter circuit arrangement includes a circuit input, a circuit output and a controllable signal source. A modulator is coupled between the signal source and the output, whilst a first logarithmic amplifier is provided having its input coupled to the circuit input. A second logarithmic amplifier is also provided having its output coupled to the circuit output. An output of each logarithmic amplifier is coupled to a respective input of a comparator, and an output of the comparator is coupled to an input of the modulator. The logarithmic amplifiers can be successive detection logarithmic amplifiers, such amplifiers having an RF output which is amplitude limited and can be designed to have constant phase limited output.

Abstract: An arbiter (7) is provided for a QMS having multiple queue users (5A to 5D), each having real time requirements for mastership of a bus (31). The arbiter (7) is arranged so that the amount of time that each queue user (5A to 5D) can gain bus access is a percentage of the total bus time.

Abstract: A method of managing data stored in a queue in memory comprises reading data from a head of the queue, and updating the location of a ‘latest read’ pointer, separate from the memory blocks in which the data is stored, to a location corresponding to the end of the data. After transferring the data to a destination and upon receiving confirmation that the data transfer was successful, the location of a ‘committed read’ pointer is updated to point to a location corresponding to the end of the data. This allows uncommitted data to be stored without requiring a separate area of memory.

Abstract: A data queue system comprises plural memory blocks defined in memory, and a queue which comprises a number of memory blocks each including a link to the following block in the data queue. A queue descriptor includes identities which identify: the final block in the queue, the memory location where the most recent read commit occurred (and optionally an offset from a predetermined location in that block), the memory location where the most recent write commit occurred (and optionally an offset from a predetermined location in that memory block), the size of the blocks, the memory location the most recent write occurred, the number of unused blocks, the number of blocks which contain data to be read, the type of data queue, the memory location where the most recent read occurred and the number of blocks which have been read since the most recent read commit.

Abstract: A method of storing a data packet in a memory divided into plural memory blocks comprises removing a header of the data packet into packet fragments, storing each packet fragment in a respective memory block with a respective header. A ‘packet start’ flag is then set in the header of the memory block containing the packet fragment corresponding to the start of the remainder of the data packet.