Abstract: An accelerometer-based mouse is one example of a device that determines the distance an object moves. The mouse disables a cursor from moving across a computer screen during movements of the mouse that occur while the mouse is lifted from a working surface. A mouse control unit generates a cursor movement disable signal that stops the cursor from moving from the time the mouse is lifted until the mouse is set down. The mouse control unit generates the disable signal by determining the derivative of an acceleration signal for the vertical (z) dimension relative to the working surface. The mouse includes a microcontroller programmed to disengage cursor movement when the cursor movement disable signal is asserted. The mouse does not include a ball and rollers whose performance can degrade as they become dirty. The mouse can detect movement even when the mouse slides over a surface that has no pattern.

Abstract: An insulative substrate includes a plurality of flexible retaining clips and a plurality of alignment and retaining pins. A metal leadframe includes a plurality of leads. Each lead terminates in a spring contact beam portion. The leadframe is attached to the substrate (for example, by fitting a hole in each lead over a corresponding alignment and retaining pin and then thermally deforming the pin to hold the lead in place). An integrated circuit is press-fit down through the retaining clips such that pads on the face side of the integrated circuit contact and compress the spring contact beams of the leads. After the press-fit step, the retaining clips hold the integrated circuit in place. The resulting assembly is encapsulated. In a cutting and bending step, the leads are singulated and formed to have a desired shape. The resulting low-cost package involves no wire-bonding and no flip-chip bond bump forming steps.

Abstract: A microcontroller has a compact 8-bit processor and a differential input sigma-delta ADC (SDADC). In a low-cost pyroelectric sensor motion detector application, a sensor output signal is supplied onto a second differential input of the SDADC. A first programmable internal reference voltage source supplies VREF1 via an internal signal path onto a first differential input of the SDADC. A second programmable internal reference voltage source supplies VREF2 onto a reference voltage input of the SDADC. VREF1 sets the center of the SDADC input sample window, thereby avoiding the need to provide an external AC blocking capacitor. VREF2 sets the size of the window. Proper window sizing and sample averaging and the high-resolution SDADC obviate the need for input signal amplification. Throughput requirements on the 8-bit processor are reduced by providing a hardware averager and associated DMA controller, thereby making the overall solution a low-cost, noise-insensitive, solution.

Abstract: A repeat instruction (RPT) operates on one or more operands, but the RPT instruction includes only an opcode and does not specify locations of the operand or operands. The type of operation to be performed when the RPT instruction is executed depends upon an initial instruction. If, for example, the initial instruction is an ADD, then the RPT instruction causes an ADC operation to be performed, thereby facilitating efficient coding of an extended precision addition operation. The locations of the operands for the RPT instruction are assumed to be in predetermined memory locations. When coding a repeated operation, rather than following the initial instruction with one or more instructions of the same form, the initial instruction is followed by one or more of the shorter RPT instructions, thereby conserving memory space and facilitating backward compatibility with an instruction set that does not have the RPT instruction.

Abstract: Clock multiplexing techniques generate an output clock signal by detecting edges of a selected input clock signal and toggling the output clock signal based on detected edges of the selected input clock signal. Toggle signals are generated based on detected edges of the selected input clock signal. Toggle signals are used to control when the output clock signal is to toggle high or low. A latch holds the state of the output clock signal in its current state until changed by receipt of a toggle signal. Switching from use of a first clock signal to use of a second clock signal occurs regardless of whether the first input clock is operating. A delay is introduced that prevents glitches in the output clock signal that are less than one half clock period of the next selected input clock signal in duration.

Abstract: A clock input filter uses a first programmable low-pass delay element to filter during a low period of an input clock signal and to output a SET signal. The clock input filter uses a second programmable low-pass delay element to filter during a high period of the input clock signal and to output a RESET signal. A latch is set and reset by the SET and RESET signals. The latch outputs a filtered version of the input signal that has the same approximate duty cycle as the input signal. A pair of gates generates a corresponding pair of duty cycle adjusted versions of the input signal. Output multiplexing circuitry is provided to output either the output of the latch, or an increased duty cycle version of the input signal, or a decreased duty cycle version of the input signal, or an unfiltered version of the input signal.

Abstract: A clock multiplexer circuit uses a delay element to detect a transition-free period in a first signal present on a D-input lead of an output latch. The output latch is then controlled to latch the stable value of the first signal, and to hold the value of the first signal on an output lead of the clock multiplexer circuit. The clock multiplexer circuit then controls a multiplexer of the clock multiplexer circuit to couple a second signal onto the D-input lead of the output latch. The clock multiplexer circuit then enables the output latch synchronously with respect to the second signal such that the output latch is made transparent at a time when the second signal on the D-input of the output latch is stable and not transitioning. The result is glitch free clock switching from the first signal to the second signal.

Abstract: A single-wire communication bus couples a transmitting device to a UART in a receiving device. Flow control circuitry in the UART fills a transmit memory buffer with remote data. The UART supplies a remote start bit onto the single-wire bus for each byte of remote data written into the transmit memory buffer. After detecting a remote start bit on the single-wire bus, the transmitting device supplies initial data bits and a stop bit, which together form an RS232 character. Data flow is controlled when the UART supplies a subsequent remote start bit only after data has been read out of the UART freeing up bytes in a receive memory buffer. After the transmitting device detects the subsequent remote start bit, the transmitting device supplies subsequent data bits onto the single-wire bus. In another embodiment, flow control circuitry functionality is performed by flow control code in the receiving device operating system.

Abstract: Program code for a processor is stored in a non-volatile memory (for example, flash memory). An individual data bit stored in a memory cell of the non-volatile memory can be changed from an unprogrammed state to a programmed state using a write cycle. An individual bit stored in the memory cannot, however, be changed from the programmed state back to the unprogrammed state without performing an erase cycle on all the bits of a page of memory cells. The processor has an instruction set that includes a multi-bit breakpoint instruction, all the bits of which are the programmed state. Because all the bits of the breakpoint instruction are the programmed state of the memory, the breakpoint instruction can be written over any other instruction that is stored in the memory without having to perform an erase cycle or erase an entire page of program code.

Abstract: A memory device includes memory cells that are overwritten in response to receipt of a clear request signal and an overwrite value. The clear request signal enables all word lines of the memory device to be overwritten. The clear request signal in combination with the overwrite value cause the overwrite value to be written to a first column of memory cells. At least two delay elements transfer the overwrite value to another column of memory cells after a delay. By use of at least two delay elements to delay and transfer the overwrite value to be written to another column of memory cells, a relatively low magnitude of current can be used to cause memory cells to be overwritten. In addition, the value and sequence of values that overwrite memory cells can be controlled.

Abstract: A point of sale terminal includes a microcontroller integrated circuit. In one aspect, a regulator within the IC receives power from a supply voltage terminal and/or a battery terminal. If the regulator does not receive adequate power from either terminal, then energy stored on-chip in a capacitor is used to erase secure memory. In another aspect, pulses of current are made to pulse through conductors of a conductive mesh. A tamper condition is detected if an improper voltage is detected on the IC terminal through which the pulse is conducted. In another aspect, each vendor signs his/her firmware with his own vendor ID. A bootloader uses the vendor ID to lookup a public key that is then used to verify a private key supplied by the firmware to be executed. In another aspect, a magnetic card reader includes a digital peak detector circuit involving programmable positive and negative thresholds.

Abstract: An integrated circuit includes an analog-to-digital (ADC) portion and a processor portion. The processor portion generates high frequency noise. The ADC portion includes chopper switches, an ADC, a first low-pass filter (LPF), an inverter, and a second LPF. An analog sensor signal is chopped by the chopper switches at a chopping frequency below the processor noise frequency. The ADC performs conversions a rate higher than the chopper frequency such that multiple first conversions are performed when the chopper switches are in a first configuration and multiple second conversions are performed when the chopper switches are in a second configuration. The first LPF attenuates the high frequency noise, converts the first conversions into first information, and converts the second conversions into second information. The inverter inverts the second information. The second LPF attenuates transposed 1/F noise and converts the first information and the inverted second information into ADC output values.

Abstract: A system efficiently expands program memory without extensively modifying the remaining microcontroller architecture. An address bus of N+M bits addresses 2N memory locations in a regular portion of program memory and additional memory locations in an expanded portion. An N-bit program counter increments through instructions stored only in the regular portion. Constants are stored in both the regular and expanded portions. An M-bit page-designator is prepended to an N-bit operand to generate a memory address of N+M bits. Program memory is expanded only when a load instruction retrieves constants from program memory. The page-designator is toggled when an N-bit operand rolls over upon incrementing by the load instruction. A block of constants straddling the boundary between the regular and expanded portions can be retrieved from program memory by executing only the load instruction. When program instructions are executed that do not retrieve constants, a fixed page-designator designates the regular portion.

Abstract: An electrostatic discharge (ESD) transistor structure includes a self-aligned outrigger less than 0.4 microns from a gate electrode that is 50 microns wide. The outrigger is fabricated on ordinary logic transistors of an integrated circuit without severely affecting the performance of the transistors. The outrigger is used as an implant blocking structure to form first and second drain regions on either side of a lightly doped region that underlies the outrigger. The self-aligned outrigger and the lightly doped region beneath it are used to move the location of avalanche breakdown upon an ESD event away from the channel region. Durability is extended when fewer “hot carrier” electrons accumulate in the gate oxide. A current of at least 100 milliamperes can flow into the drain and then through the ESD transistor structure for a period of more than 30 seconds without causing a catastrophic failure of the ESD transistor structure.

Abstract: The infrared LED of an IrDA module transmits IR energy with a peak wavelength (for example, 875 nm) appropriate for IrDA communication. This peak wavelength is lower than is the wavelength (for example, 940 nm) used in ordinary IR remote controls (RC). The IrDA LED does, however, transmit some energy at the wavelength of the peak sensitivity of an RC receiver. When making an IrDA transmission, the IrDA LED is driven with a lower amount of current. When making an RC transmission, the IrDA LED is driven with an increased amount of current such that higher wavelength emissions received by the RC receiver are of adequate power to realize RC communication. A passive circuit is disclosed for automatically increasing IrDA LED current during RC transmissions. The circuit involves an inductor that shunts current around a current-limiting resistor used to limit LED drive current.

Abstract: A portable electronic device with an IrDA transmitter LED is used to transmit both IrDA signals and remote control infrared signals. The device transmits remote control infrared signals with reduced power consumption. During a relatively longer remote control signal pulse, an inductor saturates and stores energy when a drive current flows from a power supply, through the inductor and then through the LED. An energy-transferring circuit transfers a portion of the energy stored in the inductor to the power supply. Energy is transferred when the drive current is cut and the voltage across the inductor surges, which causes an overflow current to flow through a diode in the energy-transferring circuit and to the power supply. The inductor is a planar coil of traces on a printed circuit board and therefore costs less to manufacture than does a toroidal coil of wires.

Abstract: An analog circuit of a microcontroller includes a switch that is coupled in series with a capacitor of the analog circuit. During nominal power mode operation, an operational voltage is present on the capacitor. The switch is conductive so that the capacitor is switched into the analog circuit and so that the capacitor operates as part of the analog circuit. At the beginning of sleep mode operation, the switch is made nonconductive thereby effectively switching the capacitor out of the analog circuit and storing the operational voltage on the capacitor. When the analog circuit is powered up again after sleep mode operation, the switch is made conductive to switch the capacitor back into the analog circuit. Because the capacitor still holds a substantial voltage, analog circuit wake up time is reduced because the time required to charge the capacitor up to its operational voltage is reduced.

Abstract: An IrDA module is coupled to a tapped inductor and makes both IrDA and remote control (RC) transmissions. The IrDA module includes a transmitter LED and a field effect transistor (FET) switch. The inductor has a first lead, a second lead and a tap. The first lead is coupled to a battery voltage, and the tap is coupled through a resistor to the LED anode. The drain of the FET switch is coupled to both the LED cathode and the second lead of the inductor. The location of the tap on the inductor is chosen such that the voltage drop across the LED when the FET switch is turned on and before the inductor saturates results in a desired IrDA LED drive current without using current-limiting resistors that can dissipate power. After the inductor saturates, the voltage drop across the LED results in a larger RC LED drive current.

Abstract: A “call relative counted” script instruction is interpreted by a script interpreter of an eight-bit, register-based, virtual machine. In one embodiment, the script instruction has a first argument field and a second argument field. Interpreting the script instruction causes a jump to a location identified by a label in the first argument field. After a number of script instructions identified by the second argument have been interpreted, the interpreting of script instructions automatically returns to the next script instruction after the call relative counted script instruction. In one example, the first argument is a label, the label in turn identifying the location to jump to. In another example, the first argument directly indicates the location to jump to. The instruction is useful in allowing multiple higher-level scripts to reuse different parts of a common lower-level block of script. The common block performs a common function required by the higher-level scripts.

Abstract: A microcontroller has an integrating analog-to-digital converter (IADC) with an in-situ autocalibrating functionality. On-chip autocalibrating circuitry supplies a first predetermined analog input voltage to the IADC and obtains a first data value from the IADC. The autocalibrating circuitry supplies a second predetermined analog input voltage to the IADC and obtains a second data value. The first and second data values are used to calibrate the IADC such that if the first input voltage is later supplied to the IADC, then the IADC will output a first predetermined desired digital output value and such that if the second input voltage is later supplied to the IADC, then the IADC will output a second predetermined desired digital output value. The first and second analog input voltages are generated on-chip so the calibration is performed automatically without having to supply external calibrating signals to the microcontroller. Other related methods and circuitry is disclosed.