Abstract: A method of fabricating a high performance capacitor that may be incorporated into a standard CMOS fabrication process suitable for submicron devices is described. The parameters used in the standard CMOS process may be maintained, particularly for the definition and etch of the lower electrode layer. To reduce variation in critical dimension width, an Anti-Reflective Layer (ARL) is used. In the preferred embodiment, this is of the Plasma Enhanced chemical vapor deposition Anti-Reflective Layer (PEARL) type, although other Anti-Reflective Coatings (ARCs) or layers, such as a conductive film like TiN may be employed. This ARL formation occurs after the capacitor specific process steps, but prior to the masking used for defining the lower electrodes. In one embodiment, a Rapid Thermal Oxidation (RTO) is performed subsequent to removing the unwanted capacitor dielectric layer from the transistor poly outside of the capacitor regions, but prior to the PEARL deposition.

Abstract: Remote controls sold with various audio-video equipment, such as televisions, audio amplifiers, tape players and disc players, are used to control other types of devices, such as toys and home appliances. In order to accommodate different brands of remote controls that emit infra-red control signals according to different protocols, the controlled device that is not audio-video equipment includes a universal decoder that recognizes and decodes a variety of such signals. In a preferred embodiment, the same control function that is specified for one or more keys of a remote control is carried out in the controlled device. As examples, a sound source in the controlled device is muted when a mute button of any one of many different brands of remote controls is pushed, and/or the volume of the sound source is increased and decreased when volume-up and volume-down buttons, respectively, are pushed.

Abstract: A frequency locked loop in a microcontroller integrated circuit has a precision digital feedback control loop. The frequency locked loop performs a clock multiplication function such that an inexpensive and low frequency external crystal is usable to both clock a processor of the microcontroller with a higher frequency and low-jitter clock signal and to clock a real time clock of the microcontroller with a low frequency time base that is a power of two multiple of one hertz. In one embodiment, the digital feedback control loop includes a ramp generator, a digital filter, and a loop divider. The ramp generator is controlled to output steeper and steeper ramps as the frequency locking process proceeds toward frequency lock. A preset value that presets the loop divider is changed to adjust the phase of a feedback signal with respect to a reference input signal.

Abstract: An analog-to-digital converter (ADC) exhibiting an uncorrected non-linear transfer function receives measured analog voltage amplitudes and outputs uncorrected digital values. A calibration circuit receives each uncorrected digital value and outputs a corrected digital value. The measured analog voltage amplitudes received by the ADC and the corresponding corrected digital values output by the calibration circuit define points approximating an ideal linear transfer function of the ADC. The calibration circuit performs piecewise-linear approximation of the uncorrected transfer function and associates each uncorrected digital value with the applicable linear segment that passes through a segment endpoint on the uncorrected transfer function. The calibration circuit calculates each corrected digital value using calibration coefficients associated with the applicable linear segment, such as the slope of the linear segment.

Abstract: The present invention provides a memory architecture allowing for instructions of variable length to be stored without wasted memory spaces. Instructions of one, two, and three bytes can all be retrieved in a single fetch. The exemplary embodiment divides the memory block into two ×16 memories having some special addressing circuitry. This structure logically arranges the memory into a number of rows, each of four byte-wide columns. To the first of these ×16 memories, the full address is provided. If the address is within the two columns of the second ×16 memory, the full address is also provided to the second ×16 memory. If the address is to the first of the ×16 memories, the second ×16 memory instead receives the portion of the address specifying the row with one added to it. This results in a dual row access with the last one or two bytes of 3-byte instruction being supplied by the row above the first byte.

Abstract: Universal remote control device database is updated through television video blanking interval (TV VBI) or sub-picture signal processing. As relayed through TV receiver, remote control database(s) is placed in VBI or sub-picture of video signal of specialized program. Data is decoded by VBI slicer or controller (e.g., MPEG decoder), then extracted and stored temporarily in memory. Upon request, data is transmitted via infra-red (IR) or radio-frequency (RF) emitter to learning remote control device, which downloads data to update remote programming protocol.

Abstract: Fast electromagnetic transient (EFT) events of short duration are often not detected by power-on reset circuitry of an integrated circuit (IC). A fault detector circuit involves many fault detectors. The fault detectors are distributed across the IC and may be embodied in spare cells left in a standard cell IC. Each fault detector is initialized with a digital logic value. The fault detector circuit is then controlled such that the digital logic value stored should not change if the IC is operated under normal operating conditions. An EFT event that is undetected by the power-on reset circuit may, however, cause one of the digital logic values stored in one of the fault detectors to switch. If the digital logic value stored in any one of the fault detectors switches, then a fault signal is provided to the power-on reset circuit that in turn resets the IC.

Abstract: A memory controller includes a chip-select-interface controller and a synchronous random-access-memory (SDRAM)-interface controller. The chip-select-interface controller communicates with a chip-select-interface type of memory. The SDRAM-interface controller is configured to communicate with one or more SDRAMs. The SDRAM-interface controller provides a plurality of interface signals to the SDRAM via a dedicated port. One of the interface signals, an SDRAM address/control signal, has a dual role. In one role, it serves as an address bit during memory transactions with the SDRAM. In a second role, it serves as a control signal that facilitates the refresh operation of the SDRAM.

Abstract: An Improved Signal Receiver Having Wide Band Amplification Capability is disclosed. Also disclosed is a receiver that is able to receive and reliably amplify infrared and/or other wireless signals having frequency bandwidths in excess of 40 MHz. The receiver of the present invention reduces the signal-to-noise ratio of the received signal to ?th of the prior systems. The preferred receiver eliminates both the shunting resistor and the feedback resistor on the input end by amplifying the signal in current form. Furthermore, the receiver includes transconductance amplification means for amplifying the current signal without the need for Cascode stages. Finally, the receiver includes staged amplification to amplify the current signal in stages prior to converting the signal into a voltage output.

Abstract: A single shared processing path is used as contexts are switched during processing. Each unique context is processed using a corresponding unique pipeline. If a pipeline that is executing under one context stalls, processing is switched in the shared processing path to another pipeline that is executing under second context. New pipelines are enabled for execution by borrowing a clock cycle from the currently executing pipeline. In some cases contexts are assigned various relative priority levels. In one case a context switching microprocessor is used in a communication engine portion of a system-on-a-chip communication system.

Abstract: A self-calibrating sigma-delta converter (SCADC) functions in a calibration mode and in an operational mode. In the calibration mode, a test circuit of the SCADC generates test signals that are periodic rectangular voltage waveforms. Each test signal has a dc component with a precise voltage amplitude, as well as harmonic components. A low-pass filter of a sigma-delta converter (SDC) within the SCADC filters out the harmonic components. A digital calibration processing circuit within the SCADC uses the precise voltage amplitudes to generate digital correction factors that compensate for dc offset error, gain error and INL error of the SDC. In the operational mode, the SDC receives an analog operational signal and outputs an operational digital data stream. The digital calibration processing circuit uses the correction factors to compensate for dc offset error, gain error and INL error in the operational digital data stream and outputs a corrected digital data stream.

Abstract: Non-oxidizing spacer densification method for producing semiconductor devices, such as MOSFET devices, and that may be implemented during semiconductor fabrication with little or substantially no polycide adhesion loss experienced during spacer densification. The method may be implemented to provide good polycide adhesion characteristics with reduced process complexity over conventional methods by eliminating the need for additional process steps such as metal silicide encapsulation or polysilicon surface treatments.

Abstract: An improved sigma-delta converter includes a post converter filter that receives a digital data stream. The data stream has a digital amplitude and contains quantization noise. Quantization noise is larger for digital amplitudes in a second larger-amplitude range than in a first smaller-amplitude range. The post converter filter has a higher cut-off frequency when the digital amplitude is in the first amplitude range and a lower cut-off frequency when the digital amplitude is in the second amplitude range. The post converter filter therefore filters out a portion of the larger quantization noise when the digital amplitude is larger. Quanitization noise is reduced without limiting the input signal voltage range that can be digitized.

Abstract: A method of CRT gamma correction of n-bit color and corresponding device are presented which employ a reduced size lookup table. An n-bit input signal is separated into its m most significant bits and (n−m) least significant bits. Instead of using its full n-bit value as the input address into a 2n×n lookup table, a 2m×n table employing only the m most significant bits is used, thereby reducing the memory requirements for the lookup table by a factor of 2(n−m). Every cycle, two consecutive memory locations are read, starting from where in the lookup table the m most significant bits of the input signal are pointing. The output of the lookup table provides the n-bit gamma corrected values for each of these m-bit inputs. A interpolation is then formed between these two output values and the n-bit, gamma corrected value of the full n-bit value of the input signal is then interpolated using its (m−n) least significant bits.

Abstract: Program code for a Processor is stored in a non-volatile memory (for example, flash memory). An individual data bit stored in a memory cell of the non-volatile memory can be changed from an unprogrammed state to a programmed state using a write cycle. An individual bit stored in the memory cannot, however, be changed from the programmed state back to the unprogrammed state without performing an erase cycle on all the bits of a page of memory cells. The processor has an instruction set that includes a multi-bit breakpoint instruction, all the bits of which are the programmed state. Because all the bits of the breakpoint instruction are the programmed state of the memory, the breakpoint instruction can be written over any other instruction that is stored in the memory without having to perform an erase cycle or erase an entire page of program code.

Abstract: A digital-to-analog converter (DAC) converts a digital signal into an analog signal. The DAC comprises a first capacitor network, a second capacitor network, a first amplifier, and a second amplifier. The first capacitor network includes at least one capacitor that has a weighted capacitance value. Similarly, the second capacitor network includes at least one capacitor that has a weighted capacitance value. The first amplifier has an input that couples to the first capacitor network. The first amplifier also has an output that couples to, and drives, the second capacitor network. The second amplifier has an input that couples to the second capacitor network. The output of the second amplifier constitutes the analog signal.

Abstract: A frequency locked loop in a microcontroller integrated circuit has a precision digital feedback control loop. The frequency locked loop performs a clock multiplication function such that an inexpensive and low frequency external crystal is usable to both clock a processor of the microcontroller with a higher frequency and low-jitter clock signal and to clock a real time clock of the microcontroller with a low frequency time base that is a power of two multiple of one hertz. In one embodiment, the digital feedback control loop includes a ramp generator, a digital filter, and a loop divider. The ramp generator is controlled to output steeper and steeper ramps as the frequency locking process proceeds toward frequency lock. A preset value that presets the loop divider is changed to adjust the phase of a feedback signal with respect to a reference input signal.

Abstract: Non-oxidizing spacer densification method for producing semiconductor devices, such as MOSFET devices, and that may be implemented during semiconductor fabrication with little or substantially no polycide adhesion loss experienced during spacer densification. The method may be implemented to provide good polycide adhesion characteristics with reduced process complexity over conventional methods by eliminating the need for additional process steps such as metal silicide encapsulation or polysilicon surface treatments.

Abstract: The present disclosure describes a technique for reducing east-west geometry mismatch between the top and bottom of a raster display. This is accomplished by generating a horizontal correction signal that does not have any discontinuities. Since there are no discontinuities in the horizontal correction signal, the horizontal deflection current signal will not be distorted. As a result, there will be no east-west geometry mismatch between the top and bottom of the raster display.

Abstract: A video signal is split into a first signal and a second signal. The first signal includes low amplitude/high frequency components of the video signal, which can be properly amplified by a video amplifier. The second signal includes high amplitude/high frequency components of the video signal, which cannot be properly amplified by the video amplifier. The first signal is combined with the video signal, amplified by the video amplifier, and used to modulate the intensity of an electron beam. The second signal is amplified by a scan velocity modulation amplifier and used to modulate the horizontal scan velocity of the electron beam.