Abstract: A security channel is provided for communication with an eight-bit, register-based, virtual machine. The virtual machine is placed into a direct mode, and then individual script instructions are sent to the virtual machine across the security channel for immediate interpreting by the virtual machine. The instructions are interpreted one by one as they are received. This feature can be used in debugging. This feature is usable in applications in which resident code is not required, but rather incoming script instructions are adequate to control device operation. A large memory is not required to store scripts, thereby reducing virtual machine system cost. Script instructions usable in the direct mode include instructions for loading a script API or machine code API onto the virtual machine from an external system, for loading a script, and for causing the virtual machine to output the contents of memory and/or internal registers to the external system.

Abstract: A virtual machine has a first upper level script, a second upper level script, and common block of script. The first and second scripts and the common block of script are interpreted by an interpreter of the virtual machine. The common block of script may, for example, be a script that encodes data bits in accordance with a remote control device communication protocol. The first script may include information for outputting first data bits (for example, key data). The second script may include information for outputting second data bits (for example, key data). The first script calls the common script, thereby outputting the first data in accordance with the protocol. The second script also calls the common script, thereby outputting the second data in accordance with the same protocol. Use of the common script in the outputting of the first and second data reduces memory requirements and therefore system cost.

Abstract: A System and Method for Providing an Improved Standby Mode for Infrared Data Transceivers is disclosed. Standby Mode for Infrared Data Transceivers. The device and system of the present invention includes a discovery signal receiver and power actuator module that consumes a fraction of the power of a conventional Ir transceiver system. The preferred device and system may be integral to a conventional Ir transceiver, or it may be a stand-alone system or device. Furthermore, the device and system are configured to activate full power to the Ir transceiver system upon recognition of an Ir discovery signal, and this power-up signal might also be user-initiated in some preferred embodiments. The preferred switch means for providing full power to the Ir transceiver system is in an open position while the Ir-enabled appliance is in a standby or sleep mode. The preferred device and system recognize a 9600 baud Ir discovery signal.

Abstract: A below-ground sensor interface amplifier is powered by no negative supply voltage, but the amplifier nevertheless senses an input voltage signal below ground potential. The amplifier outputs an output voltage signal that varies proportionately to the input voltage. For an input voltage beginning below ground potential and increasing past ground potential, the amplifier outputs an output voltage that remains between ground potential and a supply voltage. The output voltage increases proportionately to the increase of the input voltage. As the input voltage increases, a gate voltage on a first transistor begins to increase starting at the input voltage at which a second transistor is forced to turn on. The amplifier senses input voltages more than one threshold voltage below ground potential without using a below-ground supply voltage. The gain of the amplifier, as well as the lower limit and the size of the amplifier's voltage operating range are programmable.

Abstract: An Improved Signal Receiver Having Wide Band Amplification Capability is disclosed. Also disclosed is a receiver that is able to receive and reliably amplify infrared and/or other wireless signals having frequency bandwidths in excess of 40 MHz. The receiver of the present invention reduces the signal-to-noise ratio of the received signal to ?th of the prior systems. The preferred receiver eliminates both the shunting resistor and the feedback resistor on the input end by amplifing the signal in current form. Furthermore, the receiver includes transconductance amplification means for amplifying the current signal without the need for Cascode stages. Finally, the receiver includes staged amplification to amplify the current signal in stages prior to converting the signal into a voltage output.

Abstract: An Improved Circuit Design and Optics System for Infrared Signal Transceivers is disclosed. The preferred system includes an IR transceiver assembly that is easily grasped by assemblers. Furthermore, the primary and secondary lenses associated with the transceiver system are easier to manufacture than current lens designs. Also, the heretofore critical lens separation between the infrared emitting and infrared detection devices and the primary lens is rendered a flexible dimension, dependent only upon the particular appliance in which the system is installed. The present invention permits the stand for infrared emitting and infrared detection devices to be eliminated as a result of exchanging a non-imaging transceiver system with the current imaging transceiver system. The present invention further comprises assembling or otherwise combining infrared emitting and infrared detection devices into a single infrared emitting/infrared detection device stack.

Abstract: An on-chip oscillator generates a substantially temperature-independent clock signal by compensating for temperature-induced changes in its RC time constant and in a range between trigger voltages. A resistor with a positive temperature coefficient determines the range between trigger voltages, which increases with increasing temperature. A comparator response time contributes to a delay period that occurs after a trigger voltage is passed and before the charging or discharging of a capacitor is reversed. After the delay period, a remainder period elapses before another trigger voltage is passed. As temperature increases, the delay period is decreased by increasing a bias current supplied to the comparator. The bias current is programmably adjusted such that the sum of the delay period and the remainder period remains substantially constant over a large temperature range.

Abstract: The present disclosure describes a technique for reducing east-west geometry mismatch between the top and bottom of a raster display. This is accomplished by generating a horizontal correction signal that does not have any discontinuities. Since there are no discontinuities in the horizontal correction signal, the horizontal deflection current signal will not be distorted. As a result, there will be no east-west geometry mismatch between the top and bottom of the raster display.

Abstract: A self-calibrating sigma-delta converter (SCADC) functions in a calibration mode and in an operational mode. In the calibration mode, a test circuit of the SCADC generates test signals that are periodic rectangular voltage waveforms. Each test signal has a dc component with a precise voltage amplitude, as well as harmonic components. A low-pass filter of a sigma-delta converter (SDC) within the SCADC filters out the harmonic components. A digital calibration processing circuit within the SCADC uses the precise voltage amplitudes to generate digital correction factors that compensate for dc offset error, gain error and INL error of the SDC. In the operational mode, the SDC receives an analog operational signal and outputs an operational digital data stream. The digital calibration processing circuit uses the correction factors to compensate for dc offset error, gain error and INL error in the operational digital data stream and outputs a corrected digital data stream.

Abstract: A bandgap reference circuit (BGRC) that is suitable for low-supply voltage applications outputs an adjustable reference voltage. In an operational mode, main currents flow through diodes and are controlled by a main current generator such that a positive temperature coefficient of a voltage across a resistor compensates for a negative temperature coefficient of a voltage across the diodes. The difference of the voltages across the diodes increases with temperature and is used to generate the main currents having positive temperature coefficients. The BGRC ensures sufficient current flow through the diodes during startup. In a startup mode, a startup current generator outputs startup currents that combine with the main currents and prevent the BGRC from operating at incorrect operating points that would otherwise be stable when insufficient current flows through the diodes. The startup currents are generated when the voltage drop across the resistor is less than a predetermined voltage offset.

Abstract: A filter circuit is provided which has a filtered input and an unfiltered input. The filtered input passes through delay elements to coefficient circuitry. The unfiltered input passes to the coefficient circuitry without passing through the delay elements. In this manner, an unfiltered offset can be added to the filtered output. This filter is especially useful when the filtered value is in phase representation form; for example, when the filter value is a hue value encoded as a phase.

Abstract: A receiving device supplies a remote start bit onto a single-wire communication bus. Open-drain interfaces couple the single-wire communication bus to the receiving device and to a universal asynchronous receiver/transmitter (UART) in the transmitting device. After the UART detects the remote start bit, the UART supplies initial data bits and a stop bit onto the single-wire communication bus. The data bits, stop bit and remote start bit together form a 10-bit RS232 character. Data flow control is accomplished when the receiving device supplies a subsequent remote start bit only after accepting the initial data bits. After the UART detects the subsequent remote start bit on the single-wire communication bus, the UART supplies subsequent data bits onto the single-wire communication bus. The UART also determines a pulse duration of the remote start bit and supplies each of the data bits onto the single-wire communication bus for one pulse duration.

Abstract: An Improved Infrared Signal Communication System and Method Including Transmission Means Having Automatic Gain Control is disclosed. Also disclosed is system and method that adjusts signal transmission power in response to incident signal power amplitude. The preferred system includes a control signal loop within the signal receiving system, and the system further includes a signal transmitting system that is responsive to the control signal loop. The preferred system includes manual, semi-automatic and automatic modes of operation. Still further, the preferred method includes at least two Ir-enabled appliances “stepping” each other “down” in transmit power in response to directives issued by the other Ir-enabled appliance.

Abstract: A system for programming a remote control device incorporates a battery-powered radio frequency identification (RFID) reader into the remote control device. A passive RFID transponder is embedded into the electronic consumer device, or is otherwise provided to the consumer. The RFID transponder stores codeset data usable to control the electronic consumer device. In one example, the codeset data is an entire codeset. In another example, the codeset data is a designation of a codeset. The remote control device is placed in proximity to the RFID transponder, and a program key is pressed on the remote thereby causing the RFID reader in the remote control device to read the codeset data out of the RFID transponder and into the remote control device. In one embodiment, the codeset data is read from the RFID transponder using absorption modulation. The codeset data enables the remote control device to control the electronic consumer device.

Abstract: In an auto baud system and method, the baud rates between two communicating devices are synchronized by timing the transmission of a plurality of bits by counting the cycles of a reference clock. The number of cycles counted is then divided by the number of bits counted over and any remaining cycles are distributed evenly across the data being transmitted or received. The interface of the circuit is preferably implemented as a single pin, open drain interface which can be connected to an RS-232 communications link using external hardware.

Abstract: A method for programming a universal remote control comprises receiving a signal from a source remote control, determining characteristic information based on the signal, comparing the characteristic information to a database, determining a matching code set for the source remote control based on the comparing, and configuring the universal remote control to mimic control features of the source remote control based on the matching code set. Still other aspects and other features are also described herein.

Abstract: An on-chip oscillator generates a substantially temperature-independent clock signal by compensating for temperature-induced changes in its RC time constant and in a range between trigger voltages. A resistor with a positive temperature coefficient determines the range between trigger voltages, which increases with increasing temperature. A comparator response time is part of a delay period that occurs after a trigger voltage is passed and before the charging or discharging of a capacitor is reversed. After the delay period, a remainder period elapses before the other trigger voltage is passed. As temperature increases, the oscillator increases current supplied to a comparator to decrease the response time. Moreover, as temperature increases, the oscillator increases a charge/discharge current so that the capacitor charges and discharges faster as the range between trigger voltages increases.

Abstract: A frequency locked loop in a microcontroller integrated circuit has a precision digital feedback control loop. The frequency locked loop performs a clock multiplication function such that an inexpensive and low frequency external crystal is usable both to clock a processor of the microcontroller with a higher frequency and low-jitter clock signal and to clock a real time clock of the microcontroller with a low frequency time base that is a power of two multiple of one hertz. In one embodiment, the digital feedback control loop includes a ramp generator, a digital filter, and a loop divider. The ramp generator is controlled to output steeper and steeper ramps as the frequency locking process proceeds toward frequency lock. Ramp slope dithering is used to increase resolution. A preset value that presets the loop divider is changed to adjust the phase of a feedback signal with respect to a reference input signal.

Abstract: An analog-to-digital converter (ADC) exhibiting an uncorrected non-linear transfer function receives measured analog voltage amplitudes and outputs uncorrected digital values. A calibration circuit receives each uncorrected digital value and outputs a corrected digital value. The measured analog voltage amplitudes received by the ADC and the corresponding corrected digital values output by the calibration circuit define points approximating an ideal linear transfer function of the ADC. The calibration circuit performs piecewise-linear approximation of the uncorrected transfer function and associates each uncorrected digital value with the applicable linear segment that passes through a segment endpoint on the uncorrected transfer function. The calibration circuit calculates each corrected digital value using calibration coefficients associated with the applicable linear segment, such as the slope of the linear segment.

Abstract: An improved sigma-delta converter includes a post converter filter portion that receives digital data streams. The post converter filter portion is programmable to receive digital data streams of varying bit widths. The data streams have digital amplitudes and contain quantization noise. Quantization noise is larger for digital amplitudes in a second larger-amplitude range than in a first smaller-amplitude range. The post converter filter has a higher cut-off frequency when the digital amplitude is in the first amplitude range and a lower cut-off frequency when the digital amplitude is in the second amplitude range. The post converter filter therefore filters out a portion of the larger quantization noise when the digital amplitude is larger. Quanitization noise is reduced without limiting the input signal voltage range that can be digitized.