Abstract: The temperature for multiple devices of a memory module are determined. In one example a memory module includes a printed circuit board, a plurality of memory chips on the printed circuit board, each chip containing a plurality of memory cells and a thermal sensor, and a multiplexer on the printed circuit board, independent of the memory chips, coupled to each of the thermal sensors. A current source is coupled to the multiplexer to provide a current to each one of the thermal sensors, and a voltage detector is coupled to the multiplexer to detect a voltage from each of the thermal sensors when a current is applied. A temperature circuit is coupled to the voltage detector to determine a temperature for each memory chip based on the detected voltage.

Abstract: A method for ion implanting a tip source and drain region and halo region for a tri-gate field-effect transistor is described. A silicon body is implanted, in one embodiment, from six different angles to obtain ideal regions.

Abstract: Improved methods for performing burn-in of electronic components, such as integrated circuits (ICs) with on-board thermal sense circuits, are used to obtain a higher bin split. According to an embodiment, a thermal set-point is loaded into each IC. While the ICs are maintained at a constant elevated temperature, the burn-in system checks each IC to determine whether the set-point has been exceeded. If so, it characterizes the IC by that set-point; if not, it decrements the set-point and checks again. The method continues until all ICs have been characterized to a specific set-point. As a result of the method, a junction temperature is obtained for each IC. In addition, a real-time estimate of the burn-in time for each IC is obtained, so that burn-in time can be adjusted to maximize burn-in throughput. Apparatus for implementing improved IC burn-in is also described.

Abstract: A low power base station with a VOIP telephone line is used to combine fixed and wireless services, The device uses the Internet to communicate with a Mobile Switching Center, The base station is configured to connect to the Internet at a user-selected location and establishes a small area of wireless coverage within a greater macrocell network and providing a fixed line connection for the analog telephones at home or in the office.

Abstract: One embodiment of a method is disclosed. The method generates requests waiting for data to be loaded into a data cache including a first level cache (FLC). The method further receives the requests from instruction sources, schedules the requests, and then passes the requests on to an execution unit having the data cache. Further, the method checks contents of the data cache, replays to the requests if the data is not located in the data cache, and stores the requests that are replay safe. The method further detects the readiness of the data of bus clocks prior to the data being ready to be transmitted to a processor, and transmits an early data ready indication to the processor to drain the requests from a resource scheduler.

Abstract: A method and apparatus for pausing execution of instructions from a thread is described. In one embodiment, a pause instruction is implemented as two instructions or microinstructions: a SET instruction and a READ instruction. When a SET flag is retrieved for a given thread, the SET instruction sets a Bit flag in memory indicating that execution for the thread has been paused. The SET instruction is placed in the pipeline for execution. The following READ instruction for that thread, however, is prevented from entering the pipeline until, the SET instruction is executed and retired (resulting in a clearing of the Bit flag). Once the Bit flag has been cleared, the READ instruction is placed in the pipeline for execution. During the time that processing of one thread is paused, the execution of other threads may continue.

Abstract: A method and apparatus for a two micro-operation flow using source override. In one embodiment, the method includes the identification of a macro-instruction having one or more streaming single instruction multiple data extension type operands. Once received, the macro-instruction is decoded into a first micro-operation (uOP) and a second uOP. Once decoded, a signal is asserted to disable source operand override logic if the first micro-operation updates a logical destination register that matches a logical source register of the micro-operation. Otherwise, the mutual source override is active and executed by a register alias table (RAT) when uOP with matching logic source and destination register are detected in a same clock cycle. In doing so, macro-instructions having 128-bit operands may be processed using, for example, two uOPs (one for the lower half and one for the upper half) in a 64-bit implementation, while preserving the atomicity of the original instruction.

Abstract: A method to compress microcode utilizing a genetic algorithm includes generating a population of chromosomes, each chromosome including one or more elements that indicate a cluster to which a portion of microcode memory belongs. The method further includes determining a fitness value of each chromosome and modifying the population of chromosomes based on the fitness values of the chromosomes to generate a new population of chromosomes. In addition, the method includes compressing the microcode memory using a cluster-based compression technique, wherein clusters are selected according to a chromosome from the new population with the best fitness value. Other embodiments are also disclosed.

Abstract: A host processor and a network processor may interact effectively, particularly with edge applications that involve tasks that are best handled independently by both the host and network processors. Data may be exchanged between the processors, for example, by simply passing pointers, avoiding the need for excessive data coping.

Abstract: An optical sub-assembly (OSA) apparatus for use in an optical transmission system comprises a housing, a plurality of TO-can packaged optical devices, and a plurality of wavelength selective filters. Each of the plurality of TO-can packaged optical devices is sensitive to optical signal of one of a plurality of wavelengths. Each of the plurality of wavelength selective filters is capable of directing an optical signal of the one of the plurality of wavelengths in a pre-determined direction. The OSA apparatus can be used as one of an optical signal receiving apparatus and an optical signal transmitting apparatus.

Abstract: A method and an apparatus to sense supply voltage have been disclosed. In one embodiment, the apparatus includes a resistor having a first end and a second end, the first end coupled to a voltage supply and a ring oscillator sensor coupled between the second end of the resistor and ground, the ring oscillator sensor having an output coupled to a computational element. Other embodiments have been claimed and described.

Abstract: Disclosed is a method of forming a substrate having islands of diamond (or other material, such as diamond-like carbon), as well as integrated circuit devices formed from such a substrate. A diamond island can form part of the thermal solution for an integrated circuit formed on the substrate, and the diamond island can also provide part of a stress engineering solution to improve performance of the integrated circuit. Other embodiments are described and claimed.

Abstract: Provided are a method, system, and device to effectuate a transfer of data from one clock domain to another. In accordance with one aspect of the description provided herein, bits of data to be transferred are shifted in the first clock domain. The shifted bits of data to be transferred may be sampled in a second clock domain at a fixed time within each clock signal of the first clock domain. A stream of sampled bits may be output in the second clock domain. Additional embodiments are described and claimed.

Abstract: A method and apparatus for an event handling mechanism are described. Under an embodiment of the invention, a method comprises setting a timer for a plurality of time intervals; calling a polling function at the end of each of the plurality of time intervals, the polling function being performed by a first processor; and if the polling function results in a positive result, processing the results of the polling function with a second processor.

Abstract: According to one embodiment, a system is disclosed. The system includes an input/output (IO) frame manager (IOFM) to route received IO frames to one or more IO lists and one or more IO frame order managers (IOFOMs) to reorder frames received for each IO list according to a relative order.

Abstract: An apparatus and system includes a radiation generation device for generating radiation and a radiation detection device. A first radiation channel is optically-coupled on a first end to the radiation generation device and configured to direct the radiation generated by the radiation generation device to a second end of the first radiation channel. A second radiation channel is optically-coupled on a first end to the radiation detection device and configured to direct radiation from a second end of the second radiation channel to the radiation detection device. An optical switch is configured to selectively interrupt the transmission of radiation from the second end of the first radiation channel to the second end of the second radiation channel.

Abstract: In some embodiments an expected value is compared with a number of times a storage device has been powered up and/or spun up. A cache disassociation is detected in response to the comparing. Other embodiments are described and claimed.

Abstract: In a wireless local area network (WLAN) that includes high-throughput communication devices with multiple antennas and legacy communication devices with single antennas, training tones are transmitted over a plurality of spatial channels during a first portion of an orthogonal frequency division multiplexed (OFDM) packet-training preamble. The training tones are interspersed among subcarrier frequencies of the spatial channels. The training tones are retransmitted during a second portion of the packet-training preamble. The training tones are shifted among the subcarrier frequencies of the spatial channels during the retransmission allowing a high-throughput receiving station to perform a channel estimation on different subcarrier frequencies of the spatial channels. The legacy communication devices may receive and process the training tones and may set their network allocation vector to refrain from communicating during a subsequent interval.

Abstract: Some embodiments of the invention may incorporate an oscillator circuit into a radio frequency identification (RFID) tag in which the oscillator circuit comprises at least one component that is sensitive to an environmental factor such as temperature or humidity. When the tag responds to an RFID reader, the tag may incorporate the sense environmental parameter into its response by transmitting an oscillating signal whose frequency indicates the value of the parameter. The RFID reader may then determine the parameter by analyzing the resulting analog portion of the waveform in terms of frequency and/or cycle and/or pulse width. In some embodiments, the environmental sensor may be incorporated into the integrated circuit containing the RFID tag circuit.

Abstract: A method and apparatus for fabrication of passivated microfluidic structures is disclosed. The method includes providing a substrate having a microfluidic structure formed therein. The microfluidic structure is embedded by an embedding layer. The method further includes passivating the embedded microfluidic structure by locally heating the microfluidic structure surface in a reactive atmosphere, wherein the passivated microfluidic structure is suitable for transporting a fluid. The structure optionally further includes metal pads to form an electrokinetic pump.

Abstract: Method and system are described to determine a signal quality for nodes of a network. In one embodiment, a signal quality for nodes of a network is determined. The nodes are ranked based on the signal quality. Information from a node at a device is received; the information indicates whether the node is satisfied. In the event the node is satisfied, whether a next ranked node is satisfied is determined. In the event the node is not satisfied, network resources are allocated to the node until the node is satisfied.

Abstract: A method includes receiving a sequence of input samples that represents a row of pixels in an image. The method further includes selecting a re-scaling factor for at least a portion of the row of pixels. The method further includes determining a phase offset based on the selected re-scaling factor, and applying a direct B-spline transform to a group of the samples to generate transform coefficients. The method further includes providing the transform coefficients as an input to a filter bank, and applying the phase offset at an output of the filter bank to generate a sequence of output samples.

Abstract: A recursive carry-select substitution operation is used to optimize the design of an incrementer and similar logic devices. A carry look-ahead incrementer features XOR gates in which the XOR gates in one or more MSBs of the incrementer can be pushed back by substituting an equivalent carry-select circuit, the carry-select circuit including a multiplexer. The push back operations occur until both inputs of the XOR gates are fed by inverters, allowing an entire stage of inverters to be eliminated in the circuit. Where a bit path includes a buffer comprising two inverters, the inverter size is selected so as to execute as a single stage. The result is a carry look-ahead incrementer in which a stage is eliminated.

Abstract: A wafer may be aligned with an imaging plate including an alignment grating with a pitch P. A pupil filter in the pupil plane of the optical system may be used so that the periodicity of the intensity of light from the alignment grating is less than P at the wafer plane. Thus, an alignment pattern on the wafer having a pitch smaller than the pitch of the alignment grating may be used. For example, the intensity periodicity at the wafer plane may be P/2. In an implementation, a pupil filter may be sized and positioned to block a zero-th order maximum of light transmitted through the alignment grating at the pupil plane. The pupil filter may be sized and positioned to allow first order maxima of the light to pass. The alignment system may be used with transmission or reflection optics.

Abstract: Systems, methods, and apparatus to retarget platform interrupts in a reconfigurable system. Some embodiments include identifying each processor of a multiprocessor system capable of processing Corrected Platform Error Interrupts, adding each processor capable of processing Corrected Platform Error Interrupts to a list of potential Corrected Platform Error Interrupt targets, and updating an interrupt table with a target processor for an interrupt, wherein the interrupt table is accessible by an interrupt controller to target platform interrupts. Another embodiment includes receiving a request to disable the first processor in a multiprocessor apparatus, determining if the first processor is a Corrected Platform Error Interrupt destination, and determining if the second processor is capable of processing Corrected Platform Error Interrupts.

Abstract: Some aspects include a heat sink base, an upper metal cladded to an upper surface of the heat sink base, the upper metal defining at least one groove, and a heat sink fin disposed in the groove and secured to the upper metal. Some aspects may also include a lower metal cladded to a lower surface of the heat sink base, and a pedestal secured to the lower cladding.

Abstract: According to an embodiment of the invention, a method and apparatus for image segmentation are described. An embodiment of a method comprises inserting a state comprising a set of image segmentations into a queue, the queue being ordered by priority, the set of image segmentations having a priority representing a bound for a quality of the segmentations; extracting the state in the queue having the highest priority; if the extracted state is a terminal state, halting and outputting the extracted state as a solution; if the extracted state is not a terminal state refining the extracted state into a plurality of sets of segmentations, each of the plurality of sets having a priority, inserting the plurality of sets of segmentations into the queue, and iteratively repeating the extraction of the state in the queue having the highest priority.

Abstract: Memory apparatus and methods selectively map first lanes to second lanes. A memory agent may transfer training and return sequences using different lane mappings. The return sequences may be analyzed to identify failed lanes. Other embodiments are described and claimed.

Abstract: According to one embodiment a method for implementing bufferless DMA controllers using split transaction functionality is presented. One embodiment of the method comprises, generating a write command from a disk controller directed to a destination unit, the write command including an identifier, generating a read command from the disk controller directed to a source unit, the read command including an identifier which matches the identifier in the write command, the source unit transmitting read data on a split transaction bus, the read data including the identifier of the read command, and receiving the read data at the destination unit via the split transaction bus if the identifier of the read data matches the identifier of the write command.

Abstract: A method and system to aggregate packets. A plurality of packets are received from a medium. The packets are aggregated into a single Advanced Switching (“AS”) packet and transmitted onto an AS fabric as a single AS packet.

Abstract: A data network and a method for providing prioritized data movement between endpoints connected by multiple logical channels. Such a data network may include a first node comprising a first plurality of first-in, first-out (FIFO) queues arranged for high priority to low priority data movement operations; and a second node operatively connected to the first node by multiple control and data channels, and comprising a second plurality of FIFO queues arranged in correspondence with the first plurality of FIFO queues for high priority to low priority data movement operations via the multiple control and data channels; wherein an I/O transaction is accomplished by one or more control channels and data channels created between the first node and the second node for moving commands and data for the I/O transaction during the data movement operations, in the order from high priority to low priority.

Abstract: A method includes receiving an original string of bits where each of the bits represents one of two possible logic levels. The string of bits also carries information. A new string is formed, based on the original string, which contains all of the information of the original string by using fewer bits of one of the logic levels.

Abstract: A method and system for a configurable Vcc reference and Vss reference differential current mode transmitter is described. The system includes a Vss reference differential current mode driver, a Vcc reference differential current mode driver coupled to the Vss reference current mode driver, and a controller circuit coupled to the Vss reference differential current mode driver and the Vcc reference differential current mode driver to select between the Vss reference differential current mode driver and the Vcc reference differential current mode driver based on a type of transmission interface.

Abstract: Methods and apparatus for performing error correction code (ECC) coding techniques for high-speed implementations. The ECC code word is structured to facilitate a very fast single-error-detect (SED) that allows state machines to be stopped within a single cycle when an error is detected and enables a corresponding single-error-correct (SEC) operation to be performed over multiple cycles while the state machines are in a suspended mode.

Abstract: Subcarrier phase rotation is implemented in an OFDM transmitting apparatus to overcome problems such as, for example, non-frequency selective multipath fading. In at least one embodiment, subcarrier phase rotation is practiced in an OFDM system implementing multiple input multiple output (MIMO) techniques.

Abstract: According to an embodiment of the invention, a data controller comprises a traffic pattern collector to observe a data traffic pattern, the data traffic being comprised of data packets; a traffic service engine to receive data from the traffic controller concerning the data traffic pattern and to determine a data flow specification for the data traffic pattern, the received data including the size and arrival time of each of the data packets; and a quality of service provider to receive the data flow specification. The data flow specification is the minimum data flow specification data flow specification that will allow each of the data packets to be transferred by the traffic controller within a delay upper bound. According to one embodiment, the minimum data flow specification for the data traffic pattern is determined according to an algorithm known as the Any-Delay TB Algorithm.

Abstract: Embodiments of the present invention provide a method, apparatus and system for acquiring, by a communication device, an address sequence of an acquired packet transmitted over a communication channel and determining whether to receive the acquired packet. The method involves comparing the address sequence with one or more address sequences of previously-acquired packets stored in an address list. Then, if the address sequence does not appear in the address list, the address sequence is stored in the list. If the address sequence of the packet, match an address sequence stored in the address list, the packet is received and the and further checked to determine whether the address sequence of the packet is erroneous. Other embodiments are described and claimed.

Abstract: A method according to one embodiment may include receiving data in a receive buffer, the receive buffer comprising a plurality of buffers, and sending a hold command to a transmitting node currently sending data to hold transmission of additional data when a level of the data in the receive buffer reaches a high threshold level. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract: A method and apparatus for converting memory instructions to prefetch operations during a thread switch window is disclosed. In one embodiment, memory access instructions that are already inside an instruction pipeline when the current thread is switched out may be decoded and then converted to the complementary prefetch operations. The prefetch operation may place the data into the cache during the execution of the alternate thread.

Abstract: Methods and systems for communicating in a wireless network may use long frames each including an aggregation of medium access control (MAC) protocol data units (MPDUs). In certain embodiments, the first MPDU of a frame may be composed in a format compatible with legacy wireless local area network devices designed to read frames having only one MPDU. A field in the first MPDU may include a duration value which may be used to update a Network Allocation Vector (NAV) of the legacy device to refrain from transmitting for the duration of the long frame. Various other embodiments and implementations are also disclosed.

Abstract: Methods and apparatus to compile a software program to manage parallel ? caches are disclosed. In an example method, a compiler attempts to schedule a software program such that load instructions in a first set of load instructions has a first predetermine latency greater than the latency of the first cache. The compiler also marks a second set of load instructions with a latency less than the first predetermined latency to access the first cache. The compiler attempts to schedule the software program such that the load instruction in a third set have at least a second predetermined latency greater than the latency of the second cache. The compiler identifies a fourth set of load instructions in the scheduled software program having less than the second predetermined latency and marks the fourth set of load instructions to access the second cache.

Abstract: Briefly, a method and apparatus that may enable roaming of a station from a first access point to a second access point by presenting a power saving mode to the first access mode while establishing a secured connection with the second access point.

Abstract: A method for accessing a configuration space of a device is described. The method includes setting a first field of a packet to a value to specify a destination device, and setting a second field of the packet to a defined value to indicate that the packet is a configuration access packet. The method further includes setting a third field of the configuration access packet to a value to select one of a plurality of configuration apertures of a configuration space of the destination device, and setting a fourth field of the configuration access packet to a value to address a specific memory location within the selected aperture.

Abstract: A wireless local area network (WLAN) device transmits a header over an air interface, at a first modulation rate. The header may include an indication of a second modulation rate that will be used to transmit a consolidated payload. In one embodiment, the header includes information that enables a receiver to determine when an end of each of the multiple data units will occur. The device farther transmits the consolidated payload at the second modulation rate. The consolidated payload includes multiple data units. In one embodiment, the consolidated payload includes information that enables the receiver to determine when an end of each of the multiple data units will occur.

Abstract: The present invention is a CMOS SRAM cell comprising two access devices, each access device comprised of a tri-gate transistor having a single fin; two pull-up devices, each pull-up device comprised of a tri-gate transistor having a single fin; and two pull-down devices, each pull-down device comprised of a tri-gate transistor having multiple fins. A method for manufacturing the CMOS SRAM cell, including the dual fin tri-gate transistor is also provided.

Abstract: A method and apparatus for monitoring the performance characteristics of a multithreaded processor executing instructions from two or more threads simultaneously. Event detectors detect the occurrence of specific processor events during the execution of instructions from threads of a multithreaded processor. Specialized event select control registers are programmed to control the selection, masking and qualifying of events to be monitored. Events are qualified according to their thread ID and thread current privilege level (CPL). Each event that is qualified is counted by one of several programmable event counters that keep track of all processor events being monitored. The contents of the event counters can then be accessed and sampled via a program instruction.

Abstract: A method and system to optimize ordering of firmware modules. Optimizing the dispatch order of firmware modules reduces the boot time of a computer system. A plurality of module-to-module interfaces are collected from a plurality of firmware modules, wherein a module-to-module interface allows a first firmware module of the plurality of firmware modules to invoke a second firmware module of the plurality of firmware modules. A plurality of dependency expressions corresponding to the plurality of firmware modules are collected, wherein each dependency expression of a firmware module describes the module-to-module interfaces needed for execution of the firmware module. The plurality of firmware modules are sorted into an optimized order based on the plurality of dependency expressions and the plurality of module-to-module interfaces. In one embodiment, the plurality of firmware modules operate in accordance with an Extensible Firmware Interface (EFI) specification.

Abstract: According to one aspect of the invention, a polymer device and a method of constructing a polymer device are provided. The polymer device includes a first conductor, a second conductor, and a polymeric body between the first and second conductors. The polymeric body includes a polymer material and a phyllosilicate material.

Abstract: A display may be driven to compensate for the effects of aging on the display. In particular, the temperature of the display may be determined on an ongoing basis and utilized to further correct total integrated charge for temperature effects.

Abstract: A method, apparatus and system to enable a data processing device to operate while seemingly “off”. According to one embodiment, a data processing device is configured to recognize a new system state, i.e., Visual Off. On such a data processing device, when the power button is pressed, the request to turn off the device is intercepted by a module and the device is transitioned to a Visual Off state. To the user, this transition appears instantaneous. During the transition, audible and visual indicators on the data processing device and on human interactive devices (“HID devices”) coupled to the data processing device may be turned off and/or disabled. While in the Visual Off state, the device may be fully operational, or in an alternate embodiment, the device may be placed in a low power state. When the user presses the power button again to “wake up” the data processing device, the device may transition from Visual Off into an “on” state (“Visual On”), i.e.