Abstract: A method, apparatus, article of manufacture, and system, the method including, in some embodiments, performing an in-system (or in-the-field) self-test on a first core of a multi-core (or multi-CPU) processor to obtain at a value for at least one operational parameter of the first core, storing the value for the at least one operational parameter of the first core, testing, under control of the first core, at least one of a remaining set of cores of the multi-core processor to determine a value for the at least one operational parameter for the at least one core of the remaining set of cores, and testing, under control of the at least one core of the remaining set of cores, the first core to determine a value for the at least one operational parameter for the first core.

Abstract: According to some embodiments, an equalizer receives a signal and generates symbols based on the received signal. Moreover, a controller may be provided to determine a mode of equalizer operation based at least in part on a distribution of error associated with the symbols.

Abstract: Methods and apparatus for use with memory systems and memory modules are included among the embodiments. In exemplary systems, error-correction coding (ECC) data is temporally multiplexed with user data on the same data bus lines in a burst mode transfer, such that separate chips and data lines are not required to support ECC. The memory devices on the modules each contain additional indirectly addressable ECC segments associated with addressable segments of the device. The temporally multiplexed ECC data is read from and written to the indirectly addressable segment associated with the addressable data transmitted in the burst mode transfer. In some embodiments, two types of burst modes are supported, one which includes ECC data and one which does not. This allows one type of memory module to support both ECC and non-ECC systems, and in some cases to use ECC for some data and not for other data in the same system. Other embodiments are described and claimed.

Abstract: Provided are a method, system, and program for handling Input/Output (I/O) requests. A bus enables communication with an initiator, target device and device controller, wherein the device controller accesses the target device to execute I/O commands directed to the target device. An I/O request command is received to access the target device. The initiator is configured to transmit at least one data request on the bus to one memory address in a predefined address window of the device controller. The device controller is enabled to claim the data request to the memory address in the predefined address window from the initiator on the bus to execute the data request against the target device.

Abstract: Embodiments are generally directed to a method and apparatus for determining compatibility between devices. In one embodiment, a table including a module's parameters and rules associated therewith is obtained from a module. The rules are applied to a slot's parameters to determine the module's compatibility with the slot upon coupling to the slot.

Abstract: A multicarrier signal is generated by pre-compensating frequency-domain subcarrier symbols for substantially linear distortion subsequently introduced by a time-domain baseband filter.

Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.

Abstract: In some embodiments, transpiration cooling for passive cooled ultra mobile personal computer is presented. In this regard, an apparatus is introduced having a plurality of integrated circuit device(s), a power source to power the integrated circuit device(s), a chassis to house the integrated circuit device(s) and the power supply, and a skin to cover the chassis, the skin comprising a waterproof layer configured to prevent water from contacting the integrated circuit device(s) and a water absorbent layer configured to absorb water. Other embodiments are also disclosed and claimed.

Abstract: Various embodiments of the invention provide a frequency shifter to vary the frequency of data transmitted over time, such as to increase and decrease the frequency of test data transmitted over time to verify a digital communication device's ability to receive data having various frequencies within a specific parameter range. The frequency shifter includes a frequency modifier to shift or vary an input clock frequency to a variety of output clock frequencies, such as according to a test protocol. The frequency shifter also includes an elastic data buffer to receive the test data at the input clock frequency and to output the test data at the plurality of output clock frequencies provided by the frequency modifier.

Abstract: According to one embodiment, a built-in self test (IBIST) architecture/methodology is disclosed. The IBIST provides for testing the functionality of an interconnect (such as a bus) between a transmitter and a receiver component. The IBIST architecture includes a pattern generator and a pattern checker. The pattern checker operates to compare a received plurality of bits (for the pattern generator) with a previously stored plurality of bits.

Abstract: A variable gain amplifier includes multiple gain stages. Each gain stage includes a gain transistor and a cascode transistor to form a cascode amplifier, and a current diversion transistor to divert current away from a cascode transistor to reduce gain in the stage. A control circuit is included to maintain substantially constant drain-to-source voltage and drain current in the gain transistor.

Abstract: A system includes a lift chair having sensors embedded therein to determine various factors such as the amount of pressure exerted in various portions of the chair, the activity level of the chair user, whether the chair is occupied and which user is currently occupying the chair, and how much assistance the chair provides the user. The information detected by the sensors can be transmitted via the Internet, for example, to a third party device, such as a doctor's personal computer, which is also hooked up to the internet and is capable of receiving periodic updates to monitor use of the chair or modify the rules that govern the use of the chair. The user can override the pre-set rules for use of the chair by using an override button on a user control device.

Abstract: An array capacitor is described for use with an integrated circuit (IC) mounted on an IC package. The array capacitor includes a number of first conductive layers interleaved with a number of second conductive layers and a number of dielectric layers separating adjacent conductive layers. The array capacitor further includes a number of first conductive vias to electrically connect the first conductive layers and a number of second conductive vias to electrically connect the second conductive layers. The array capacitor is provided with openings which are configured to enable pins from an IC package to pass through.

Abstract: A method is disclosed for mitigating narrowband interference within a system for wideband communications. The method can include separating a wideband signal into a plurality of sub bands, detecting energy levels in the sub-bands, and activating a control signal if the energy levels of the sub-bands differ by a predetermined amount. Such a difference in energy levels can indicate that narrowband interference is present and interference mitigation features can be activated. In another embodiment, a system is disclosed that has a band splitter and a plurality of energy level detectors to detect energy differences in the sub bands. Other embodiments are also disclosed.

Abstract: A circuit board is described where the fiberglass fiber pattern as been modified than what is found in conventional FR4 circuit boards. In one embodiment, the sets of fiberglass fibers are disposed in a zig-zag or herringbone manner. In one use, when a pair of conductors are disposed onto or into the board, the material surrounding a first conductor tends to be similar to the material surrounding a second conductor. Doing so may reduce differential to common mode conversion between the conductors.

Abstract: Numerous embodiments of a method and apparatus for address management in a network device are disclosed.

Abstract: An access point may use two omni-directional antennas or one omni-directional antenna and multiple sectored antennas in a communications network. The mobile stations may use sectored antennas. The omni-directional antennas may include two or more sectored antennas.

Abstract: Network bundles may be processed in a distributed network having a decentralized serving structure. The message bundles may be modified to include a client address. Additionally, each message bundle comprises a plurality of sub-messages, and each sub-message may contain either a link to the output of another sub-message, or a network address. A network device may be implemented to gather responses to the sub-messages from various servers and to organize the responses into a final response to send to the client.

Abstract: A barrier and seed layer for a semiconductor damascene process is described. The seed layer is formed from a noble metal with an intermediate region between the barrier and noble metal layers to prevent oxidation of the barrier layer.

Abstract: In some embodiments, an circuit card includes an electronic circuit substrate, a ground plane on the electronic circuit substrate, first and second differential signal pads on the electronic circuit substrate, a ground return signal pad associated with the first and second differential signal pads, the ground return signal pad being connected to the ground plane on the electronic substrate, and a cutout structure on the ground plane positioned near a location where the ground return signal pad connects to the ground plane, wherein the cutout structure is configured to direct a ground return path associated with the first and second differential signal pads to the ground return signal pad associated with the first and second differential signal pads. Other embodiments are disclosed and claimed.

Abstract: A method and apparatus for managing memory for time division multiplexed high speed data traffic is provided. The method and apparatus utilize an interleaving approach in association with multiple memory banks, such as within SDRAM, to perform highly efficient data reading and writing. The design issues a first command or access command, such as a read command or write command to one memory bank, followed by an active command to a second memory bank, enabling efficient reading and writing in a multiple data flow environment, such as a SONET/SDH virtual concatenation environment using differential delay compensation.

Abstract: In some embodiments an apparatus includes an amplifier, a first inverter having an input coupled to an output of the amplifier, and a second inverter having an input coupled to an output of the first inverter and an output, where the output of the second inverter is fed back to an input of the amplifier. Other embodiments are described and claimed.

Abstract: A method of maintaining network protocol timers in data structures associated with different respective processors in a multi-processor system. The timers accessed by a respective one of the processors include timers of connections mapped to the processor.

Abstract: A memory read request is received at a port from a device, wherein the port is connected to the device by a packet-based link. The memory read request is enqueued into a small request queue or a large request queue based on an amount of data requested in the memory read request. Memory read requests are interleave dequeued between the small request queue and the large request queue based on an interleave granularity.

Abstract: Conference calls are handled using distributed processing. In one embodiment, the invention includes receiving sets of telephone audio signals from conference subnodes, the telephone audio signals corresponding to subscribers of the conference call, selecting an output set of telephone audio signals from all of the received telephone audio signals, and transmitting the output set to the conference subnodes. In another embodiment, the invention includes receiving a set of telephone audio signals, each signal being received from a subscriber node of a single conference call, selecting a subset of the set of signals, transmitting the selected subset of signals to a conference node, receiving a second set of telephone audio signals from the conference node, and transmitting the second set to the subscriber nodes.

Abstract: Briefly, in accordance with one embodiment of the invention, a wireless communication system may adaptively switch between a multiple input, multiple output mode and a spatial division, multiple access mode based at least in part on channel conditions and traffic conditions.

Abstract: According to some embodiments, content filtering is provided for a digital audio signal.

Abstract: A pumping medium for an electro-osmotic pump made of porous silicon. The porous silicon may result in a lower required pumping voltage and a smaller form factor for an equivalent flow rate and pressure generation as compared to conventional glass frits. The porous silicon may also provide a better thermodynamic efficiency over conventional glass frits for use in electro-osmotic pumps. The increased efficiency of the porous silicon may provide an low-power, high flow rate, high pressure, small form factor, vibration-free pump for cooling microelectronic devices, such as integrated circuit chips.

Abstract: Transmission of digital signals across a bus between an electronic device having a transmitter and another electronic device having a receiver with termination for both the transmitter and receiver being referenced to ground, such that the electronic device having the transmitter and the other electronic device having the receiver are able to be powered with differing decoupled voltages, such that the voltage employed by the electronic device having the transmitter is able to be lower than the voltage employed by the other electronic device having the receiver, and wherein the electronic device having the transmitter may transmit addresses and/or commands to the other device having the receiver using single-ended signaling, while both electronic devices may exchange data using differential signaling.

Abstract: A modified EUV photoresist and a method of making the resist. The modified resist includes an EUV photoresist and a LAM incorporated into the EUV photoresist.

Abstract: Briefly, an adaptive transmitted power control scheme, which may be used in stations of a communication system, for example, a wireless communication system. The scheme may allocate transmission power to a communication station based on multiplying each of at least one transmitted subcarrier complex number by a corresponding subcarrier weight. Additionally, a detection scheme may detect whether a transmitted power control scheme according to an embodiment of the invention is used by stations of the communication system. The allocation of transmission power may be also used to transmit additional service information through channels.

Abstract: A method and related apparatuses support booting despite deficient system resources. In one embodiment, a processing system includes two or more devices in a peripheral connect interface (PCI) subsystem, as well as instructions encoded in a machine accessible medium. The instructions, when executed during a process of booting the processing system, may determine whether sufficient resources are available for the devices. The instructions may also retrieve boot information from an extended firmware interface (EFI) environment of the processing system, and may automatically identify a device as boot-critical, based on that boot information. The instructions may also identify a device to be rejected, and may automatically allocate resources for the boot-critical device but not for the rejected device, before the processing system boots the OS, if sufficient resources for the devices are not available. Other embodiments are described and claimed.

Abstract: According to some embodiments, a connector to receive a memory module includes a first row of a first plurality of interconnect ends, a second row of a second plurality of interconnect ends adjacent to the first row, and a third row of a third plurality of interconnect ends adjacent to the second row. An interconnect end of the first plurality of interconnect ends, an interconnect end of the second plurality of interconnect ends, and an interconnect end of the third plurality of interconnect ends may be substantially aligned.

Abstract: An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a program at a first performance level. The first core stops executing the program when a triggering event occurs. A second core has a second instruction set compatible with the first instruction set and has a second performance level different than the first performance level. The second core is in a power down state when the first core is executing the program. A circuit powers up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level.

Abstract: Provided are a method, system, and program for constructing a packet. A request to construct one packet is received, including information on at least one header and a payload to include in the packet. The at least one header for the received request is generated and the generated at least one header is written in a first queue. The payload is requested to include in the packet and the received payload is written to a second queue. The generated at least one header and payload are read from the first and second queues and the read at least one header and payload are included in the packet.

Abstract: Methods and apparatus for finding a shared secret without compromising non-shared secrets are disclosed. The methods and apparatus receive a first group of hashed secrets from a communication device and compare the first group of hashed secrets to a second group of hashed secrets associated with an application server. A shared secret is identified among the first and second groups of hashed secrets. An application associated with the shared secret is sent to the communication device via a communication channel.

Abstract: An imaging structure such as a mask or reticle may be fabricated using a patterning layer on an imaging layer. The patterning layer may have substantially different etch properties than the imaging layer. A first etch process may be selective of the patterning layer with respect to a resist layer. A second etch process may be selective of the imaging layer with respect to the patterning layer.

Abstract: A chassis includes a plurality of slots to receive modules. The chassis further includes a first backplane to couple to modules that are received in the plurality of slots. The modules are to couple to the first backplane via a first communication interface on each module. The chassis also includes a second backplane to couple to at least a subset of the modules via a second communication interface on each of the subset of modules. One of the backplanes may be located in an upper or lower air plenum and used to interconnect modules slid along the slots from opposite directions. Some of the module connectors may be retractable to enable the modules to move into the chassis. The interface may be electrical, optical inductive or capacitive.

Abstract: Briefly, some embodiments of the invention may provide devices, systems and methods for thermal control. For example, a method in accordance with an embodiment of the invention may include modifying an operational parameter of a processor based on a temperature of a heat sink associated with the processor.

Abstract: Alloy memory structures and methods are disclosed wherein a layer or volume of alloy material changes conductivity subsequent to introduction of a electron beam current-induced change in phase of the alloy, the conductivity change being detected using current detection means such as photon-emitting P-N junctions, and being associated with a change in data bit memory state.

Abstract: A method and apparatus for providing, in a processor, a shift operation on a packed data element having multiple values. One embodiment of a central processing unit (CPU) includes instruction fetch logic to fetch a single-instruction-multiple-data (SIMD) shift instruction. A register stores a multiple data elements to be operated upon by the SIMD shift instruction. A barrel shifter concurrently shifts the data elements in a bit-wise manner by a variable number of bit positions in response to the SIMD shift instruction.

Abstract: Provided are a method, system and program for buffering writes to an Input/Output (I/O) device in a cache. Writes to an Input/Output (I/O) device are buffered in a cache. Information on the buffered writes are communicated to a monitor component enabling identification of the buffered writes in the cache. A system failure is detected. The monitor component determines from the information on the buffered writes buffered in the cache that have not been transferred to the I/O device in response to the system failure. The monitor component causes the transfer of the determined writes to the I/O device.

Abstract: In one embodiment, the invention is an apparatus. The apparatus includes a pair of parallel traces on a first level of a PCB (printed circuit board). The apparatus also includes a stub on a second level of the PCB. The stub is parallel to the pair of parallel traces. The stub is physically disconnected from the pair of parallel traces. The stub has a predetermined length based on an expected frequency. The stub is formed of an electrically conductive material.

Abstract: Systems and methods employing a flexible mesh structure for hierarchical scheduling are disclosed. The method generally includes reading a packet grouping configured in a two dimensional mesh structure of N columns, each containing M packets, selecting and promoting a column best packet from each column to a final row containing N packets, reading, selecting and promoting a final best packet from the final row to a next level in the hierarchy. Each time a final best packet is selected and promoted, the mesh structure can be refreshed by replacing the packet corresponding to the final best packet, and reading, selecting and promoting a column best packet from the column containing the replacement packet to the final row. As only the column containing the replacement packet and the final row are read and compared for each refresh, the mesh structure results in reduced read and compare cycles for schedule determination.

Abstract: A method is disclosed for interference mitigation which can include receiving a signal having a data component, an interfering component and a time period and creating a first plurality of digitized data that represents at least a portion of the interfering component. The method can also include generating a polynomial equation that is related to the at least a portion of the interfering component and generating a second plurality of digital data that represents a data vector of the received signal. The method can further subtract the polynomial equation from the received signal to cancel at least a portion of the interfering component to provide an interference mitigated signal representing the data component.

Abstract: A method is disclosed that includes receiving a signal having a data vector component and an interfering component and creating a first set of digitized data that represents the interfering component. The method can also generate a polynomial equation based on the first set of digitized data and generate a second set of digitized data that represents a data vector component of the received signal. The polynomial equation can be subtracted from the received signal to cancel at least a portion of the interfering component and provide an interference mitigated signal representing the data vector component. An error in the interference mitigated signal can be determined and the interference mitigated component can be recalculated based on the error. Other embodiments are also disclosed.

Abstract: Disclosed is a method for handling conflicting deadlines by a disk drive. The method comprises: receiving a plurality of requests from a plurality of applications for accessing the disk drive; determining a plurality of service times for the plurality of requests; serving a first request of the plurality of request prior to an actual schedule when a deadline for serving the first request and a deadline for serving a subsequent request of the plurality of requests cannot be simultaneously met by the disk drive; and serving the subsequent request after the first request is served by the disk drive.

Abstract: In some embodiments a method is disclosed for detecting periodic interference and predicting future interference times. The method can include detecting an arrival time of a first occurrence of interference and detecting an arrival time of a second occurrence of interference. The method can include transmitting preemptive interference mitigation control signals that anticipate future arrival times of interference. A system is disclosed that includes a periodicity detector, an interference profiler and a mitigation control module. The system can provide interference mitigation features to a data recovery system. Other embodiments are disclosed.

Abstract: On-die coupled inductor structures are disclosed that are capable of reducing the occurrence of charge crowding within the structure.

Abstract: According to embodiments of the present invention, an optical transponder includes a transmitter optical subassembly (TOSA). In one embodiment, the electrical ground of the TOSA may be DC-isolated from chassis ground of the transponder using a blocking capacitor that couples the AC signal path to VDD and that allows the case of the TOSA to float. In an alternative embodiment, the electrical ground of the TOSA may be DC-isolated from chassis ground of the transponder using a blocking capacitor that couples the AC signal path to VDD and a resistor that couples the DC bias level path to internal electrical ground or transponder case ground.