Abstract: In one embodiment, the present invention includes a method for generating an assembly that is usable in a managed environment. More specifically, the assembly may be an all-inclusive object file that contains a native code module, a managed wrapper and prototype information in a single assembly. The method may include forming an object file from a native code module, where the object file includes prototype information, generating a managed code wrapper using the prototype information, and creating a single assembly including the managed code wrapper and the native code module. In some embodiments, the managed code wrapper may be automatically created, reducing burden on a developer. Other embodiments are described and claimed.

Abstract: Embodiments of methods in accordance with the present invention provide three-dimensional carbon nanotube (CNT) integrated circuits comprising layers of arrays of CNT's separated by dielectric layers with conductive traces formed within the dielectric layers to electrically interconnect individual CNT's. The methods to fabricate three-dimensional carbon nanotube FET integrated circuits include the selective deposition of carbon nanotubes onto catalysts selectively formed on a conductive layer at the bottom of openings in a dielectric layer. The openings in the dielectric layer are formed using suitable techniques, such as, but not limited to, dielectric etching, and the formation of ring gate electrodes, including spacers, that provide openings for depositing self-aligned carbon nanotube semiconductor channels.

Abstract: A correction for photolithography masks used in semiconductor and micro electromechanical systems is described. The correction is based on process windows. In one example, the invention includes evaluating a segment of an idealized photolithography mask at a plurality of different possible process variable values to estimate a corresponding plurality of different photoresist edge positions, comparing the estimated edge positions to a minimum critical dimension, and moving the segment on the idealized photolithography mask if the estimated edge positions do not satisfy the minimum critical dimension.

Abstract: An embodiment of the present invention provides a network interface card (NIC), comprising an intelligent wake mechanism and a device driver associated with the intelligent wake mechanism and configured to agree with embedded software on a set of wake codes and wake behaviors associated with the wake codes such that when the NIC encounters a wake event, the NIC first adds the wake code to a command queue, then it drives a PME pin to high to wake a device connected to the NIC.

Abstract: Machine-readable media, methods, and apparatus are described to issue transactions to a memory. In some embodiments, a memory controller may select pending transactions based upon selection criteria and may issue the selected transactions to memory. Further, the memory controller may close a page of the memory accessed by a write transaction in response to determining that the write transaction is the last write transaction of a series of one or more write transactions.

Abstract: Methods and arrangements to establish power rails for a computer system in accordance with a sequence requirement are disclosed. Embodiments may interconnect voltage regulators for components of a platform in accordance with a sequence requirement for establishing power rails for proper operation of the platform. The voltage regulators may comprise enable inputs for enabling the establishment of power rails and power good signal outputs to indicate establishment of power rails. Some embodiments include interconnections to couple voltage regulators in a series of stages. Power good signals output by voltage regulators in one stage may enable inputs of voltage regulators in a subsequent stage. In many embodiments, such interconnections advantageously implement power sequence requirements with little or no need for glue logic and/or programmable logic devices, reducing costs and space requirements associated with implementing the power sequence. Other embodiments are disclosed and claimed.

Abstract: Elongated features may be incorporated at least partially in an alignment region. The alignment region may be defined by a plurality of alignment features aligned along a first axis. A long axis of the elongated features may be neither parallel nor perpendicular to the first axis. The alignment region may further include another plurality of alignment features aligned a second axis that is not parallel to the first axis. The second axis may be neither parallel to or perpendicular to the long axis.

Abstract: Operands may be assigned to physical registers within partitioned register banks by identifying possible candidate register banks for an operand. Prior to allocation of the operand to a candidate register bank, conflicts between candidate register banks, if any, may be identified and resolved.

Abstract: According to embodiments of the present invention, an external cavity laser includes one or more tuning elements. At least one modulated voltage signal or dither is used to lock the transmission peak of the two tuning elements to each other. The wavelength of the laser also may lock onto the lock transmission peaks. In embodiments in which two dither signals are used, the dither signals may be orthogonal to or independent of each other. The two dither signals may produce two control signals to align the transmission peak of one filter to the transmission peak of another filter and the lasing mode of the laser to the aligned filters.

Abstract: An imaging structure such as a mask or reticle may be fabricated using a patterning layer on an imaging layer. The patterning layer may have substantially different etch properties than the imaging layer. A first etch process may be selective of the patterning layer with respect to a resist layer. A second etch process may be selective of the imaging layer with respect to the patterning layer.

Abstract: An article of manufacture includes a circuit board and a pair of traces on or in the circuit board. The pair of traces includes a first trace and a second trace. The first trace includes a first segment and a second segment continuously joined to the first segment. The first segment coincides with a first longitudinal axis. The second trace includes a first segment that runs alongside the first segment of the first trace. The second trace also includes a second segment that runs alongside the second segment of the first trace. The second segment of the second trace is continuously joined to the first segment of the second trace. The second segment of the second trace coincides with the first longitudinal axis.

Abstract: A computer system is partitioned during a pre-boot phase of the computer system between a first partition and a second partition, wherein the first partition to include a first processing unit and the second partition to include a second processing unit. An Input/Output (I/O) operating system is booted on the first partition. A general purpose operating system is booted on the second partition. Network transactions are issued by the general purpose operating system to be performed by the I/O operating system. The network transactions are performed by the I/O operating system.

Abstract: Queuing command information is stored in a content addressable memory (CAM) where a queuing command for a first queue is received, the CAM is examined to determine if commands for the first queue are present, and if commands for the first queue were found to be present, information is stored in a linked list for the received command in multiple CAM entries.

Abstract: An inter-layer dielectric structure and method of making such structure are disclosed. A composite dielectric layer comprising a porous matrix, as well as a porogen in certain variations, is formed adjacent a sacrificial dielectric layer. Subsequent to other processing treatments, a portion of the sacrificial dielectric layer is decomposed and removed through a portion of the porous matrix using supercritical carbon dioxide leaving voids in positions previously occupied by portions of the sacrificial dielectric layer. The resultant structure has a desirably low k value as a result of the voids and materials comprising the porous matrix and other structures. The composite dielectric layer may be used in concert with other dielectric layers of varying porosity, dimensions, and material properties to provide varied mechanical and electrical performance profiles.

Abstract: Methods for forming a wire from silicon or other semiconductor material are disclosed. Also disclosed are various devices including such a semiconductor wire. According to one embodiment, a wire is spaced apart from an underlying substrate, and the wire extends between a first end and an opposing second end, each of the first and second ends being affixed to the substrate. Other embodiments are described and claimed.

Abstract: An embodiment of the present invention is a technique to package flip chip molded matrix array package. An ultraviolet (UV) curable tape is laminated on die backside of a strip of array of flip chips. The UV curable tape has an adhesive strength. The strip of flip chip arrays is molded with a mold film. The molded strip of flip chip array is irradiated using UV radiation. In another embodiment, a double functional tape is mounted to backside of a wafer. The double functional tape includes a binding tape and a ultraviolet (UV) curable tape having an adhesive strength. The wafer is singulated into die. The die is attached to a substrate strip to form a strip of array of flip chips. The strip is molded with a mold film. The molded strip is irradiated using UV radiation.

Abstract: A method and apparatus are provided for executing packed data instructions. According to one aspect of the invention, a processor includes registers, a register renaming unit coupled to the registers, a decoder coupled to the register renaming unit, and a partial-width execution unit coupled to the decoder. The register renaming unit provides an architectural register file to store packed data operands that include data elements. The decoder is to decode a first and second set of instructions that each specify one or more registers in the architectural register file. Each of the instructions in the first set specify operations to be performed on all of the data elements. In contrast, each of the instructions in the second set specify operations to be performed on only a subset of the data elements. The partial-width execution unit is to execute operations specified by either the first or second set of instructions.

Abstract: A data structure for use in database applications. The data structure includes a key database that is searchable via an index table.

Abstract: Mechanical stresses are reduced between an electronic component having relatively low fracture toughness and a substrate having relatively greater fracture toughness. In an embodiment, the component may be a die having mounting contacts formed of a low yield strength material, such as solder. A package substrate has columnar lands formed of a relatively higher yield strength material, such as copper, having a relatively higher melting point than the component contacts and having a relatively high current-carrying capacity. The component contacts may be hemispherical in shape. The lands may be substantially cylinders, truncated cones or pyramids, inverted truncated cones or pyramids, or other columnar shapes. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.

Abstract: An embodiment of the present invention is a technique to functionalize carbon nanotubes in situ. A carbon nanotube (NT) array is grown or deposited on a substrate. The NT array is functionalized in situ with a polymer by partial thermal degradation of the polymer to form a NT structure. The functionalization of the NT structure is characterized. The functionalized NT structure is processed according to the characterized functionalization.

Abstract: A method for managing thermal condition of a thermal zone that includes multiple thermally controllable components include determining thermal relationship between the components and reducing temperature of a first component by reducing thermal dissipation of a second component.

Abstract: A fast lock scheme for phase locked loops and delay locked loops, where apparatus, systems, and methods include a startup circuit that is enabled at the beginning of a startup mode and is disabled upon a phase transition detection in the reference and feedback signals to the phase locked loop or delay locked loop. Further apparatus, systems, and methods enable a first charge pump when a phase transition is detected, and enable a second charge pump when the phase difference between the reference and feedback signals fall within a predetermined range.

Abstract: The present invention relates to a Tunnel Field Effect Transistor (TFET). which utilizes angle implantation and amorphization to form asymmetric source and drain regions. The IFET further includes a silicon germanium alloy epitaxial source region with a conductivity opposite that of the drain.

Abstract: A digital content pricing apparatus may include a sales computer and a memory used to retain digital content items associated with a base price and one or more option prices, along with a final price related to the base and option prices by a final pricing formula. A method may include selecting a digital content item and at least one configuration option associated with the item, calculating the item price using appropriate adjustment factors, and calculating the final price using a final pricing formula. Pricing information, in the form of prices, adjustment factors, and formulae may be defined in meta-data descriptors included in the digital content.

Abstract: A system, apparatus, and method are provided for entitlement security and control. According to one embodiment, an entitlement request is received from a downstream access control system seeking entitlement permission on behalf of a user, a group of users, all users associated with the downstream access control system, or on behalf of the downstream access control system as a whole, the entitlement request is matched against entitlement rules and roles that are retrieved from a metadata repository, and the entitlement permission is granted if the entitlement request satisfies the entitlement rules and roles.

Abstract: The methods, compositions and apparatus disclosed herein are of use for nucleic acid sequence determination. The methods involve isolation of one or more nucleic acid template molecules and polymerization of a nascent complementary strand of nucleic acid, using a DNA or RNA polymerase or similar synthetic reagent. As the nascent strand is extended one nucleotide at a time, the disappearance of nucleotide precursors from solution is monitored by Raman spectroscopy or FRET. The nucleic acid sequence of the nascent strand, and the complementary sequence of the template strand, may be determined by tracking the order of incorporation of nucleotide precursors during the polymerization reaction. Certain embodiments concern apparatus comprising a reaction chamber and detection unit, of use in practicing the claimed methods. The methods, compositions and apparatus are of use in sequencing very long nucleic acid templates in a single sequencing reaction.

Abstract: A compact PCB connector is disclosed to facilitate connection between various components of computer system. The PCB connector comprises a housing having a front side adjacent to the bottom side of the housing. A plurality of connectors supported by the housing are provided to facilitate connection between the various components of a computer system.

Abstract: Wireless communication devices and methods for coordinated channel access with reduced latency in a wireless network are generally described herein. Other embodiments may be described and claimed.

Abstract: A voltage regulator is described for microelectronic devices using dual edge pulse width modulated control signal. In one example a first digital duty cycle value is received from a voltage controller and a pulse width modulated waveform is generated in response to the first duty cycle value, the waveform comprising a plurality of pulses with a modulated width. The waveform is applied to a voltage generator to generate a supply of power at a voltage determined by the duty cycle of the waveform. A second digital duty cycle value is received from the controller, and the leading edge of a subsequent pulse of the waveform is advanced if the second digital duty cycle value is greater than the first digital duty cycle. The trailing edge of the subsequent pulse of the waveform is advanced if the second digital duty cycle value is less than the first digital duty cycle value.

Abstract: Provided are a techniques for mapping data blocks to storage blocks. A portion of data is received, and the portion of data is segmented into one or more data blocks. The one or more data blocks are mapped to one or more storage blocks of one or more storage devices, wherein the one or more data blocks are mapped to wrap around the storage devices after each of the storage devices has been utilized.

Abstract: Apparatuses, methods, and articles of manufacture disclosing a filter with a plurality of convolver branches are described herein. Each of the plurality of convolver branches include a multiplier, integrator, and sampler and hold circuit. A sampled output of one branch may be fed back to another branch. Other embodiments may be described and claimed.

Abstract: A method of controlling a social network access control list (ACL) for a shared resource includes monitoring communications to and from a user. Social network data from the communications to and from the user is determined. An access level for the user is determined based on the social network data. The access control list is configured to provide the user the access level determined for accessing the shared resource.

Abstract: The present disclosure relates to the resource management of virtual machine(s) using hardware address mapping, and, more specifically, to facilitate direct access to devices from virtual machines, utilizing control of hardware address translation facilities.

Abstract: Various methods, apparatuses and systems are described in which a skew delay time between communication lanes is determined. A data transfer path is established which includes two or more communication lanes in a communication link. A skew delay time is determined between the communication lanes of the communication link with respect each other with using a clock period of a input output circuit as a reference time.

Abstract: Provided are a method, system, program and device for maintaining shadow page tables in a sequestered memory region. A first processor executing an application invokes a second processor to create a shadow page table used for address translation for the application in a sequestered memory region non-alterable by processes controlled by an operating system executed by the first processor. The shadow page table references at least one page in an operating system memory region accessible to processes controlled by the operating system.

Abstract: A clock network comprises a clock distribution path coupled to a circuit. The clock distribution path and the circuit are formed on a substrate. The clock distribution path comprises a plurality of interconnected elements and one or more disconnected elements. The disconnected elements can be connected to the plurality of interconnected elements after the clock distribution path is tested in connection with the circuit. In one embodiment, the disconnected elements include a capacitor, an interconnect, and a buffer. In an alternative embodiment, the plurality of interconnected elements include a buffer, an interconnect and a capacitor.

Abstract: Methods and apparatus to manage bypassing of a first cache are disclosed. In one such method, a load instruction having an expected latency greater than or equal to a predetermined threshold is identified. A request is then made to schedule the identified load instruction to have a predetermined latency. The software program is then scheduled. An actual latency associated with the load instruction in the scheduled software program is then compared to the predetermined latency. If the actual latency is greater than or equal to the predetermined latency, the load instruction is marked to bypass the first cache.

Abstract: An embodiment of the present invention is a technique to functionalize carbon nanotubes in situ. A carbon nanotube (NT) array is grown or deposited on a substrate. The NT array is functionalized in situ with a polymer by partial thermal degradation of the polymer to form a NT structure. The functionalization of the NT structure is characterized. The functionalized NT structure is processed according to the characterized functionalization.

Abstract: In some embodiments, an adhesive system for supporting thin silicon wafer is presented. In this regard, a method is introduced to bond a silicon wafer to a translucent carrier through the use of an adhesive. Other embodiments are also disclosed and claimed.

Abstract: A method and architecture for enabling interaction between a remote device and a host computer. A service provided by the remote device is discovered, and a description pertaining to the service is retrieved by the host computer. A network communication link is the established between the remote device and the host computer based on connection information provided by the description. Host-side and client-side software service modules are run on the host and remote devices to enable interaction between the devices using a service protocol that is specific to the service. Various service protocols are provided, including a display service protocol and an input service protocol. Using commands provided by each protocol, the host computer is enabled to control the service remotely by pushing data and appropriate commands to the remote device, whereupon these commands are processed by the client-side service module to perform service operations that employ the sent data.

Abstract: In some embodiments, a method, apparatus and system to detect and signal sequential hot plug failure diagnostics are presented. In this regard, a diagnostic agent is introduced to store a plurality of bits corresponding to a hot plug error code in a register sequentially such that a plurality of hot plug error codes can be stored in the register. Other embodiments are also disclosed and claimed.

Abstract: Systems and methods of thermal management provide for dynamically the upper and lower operating points of a throttled device such as a processor. In one embodiment, it is determined that the temperature of the processor is below a threshold and moving the upper operating point and the lower operating point toward one another.

Abstract: In a multiprocessor, access to shared resources is provided by a semaphore control mechanism, herein disclosed. The semaphore control mechanism provides for a high degree of programmable firmware reuse requiring relatively few modifications from a uniprocessor. The semaphore control mechanism receives one or more semaphore modification requests from one or more requesting devices, identifies an ownership state of a semaphore corresponding to the one or more semaphore modification requests, arbitrates to identify modification request from a particular requesting device to succeed if the identified ownership state corresponds to the particular requesting device or if the identified ownership state corresponds to no ownership.

Abstract: A method of sensing data in a multi-level cell memory using two or less sense operations and adjusting column load is provided. A sensing circuit implementing a serial-parallel sense scheme is also provided. The column loads are re-configurable based on the sensing circuit and the serial-parallel sense scheme.

Abstract: Apparatuses and methods for dynamically adjusting carrier sensing threshold levels in a wireless, such as CSMA, system. A station may use the carrier sensing measurement made in normal CSMA operation to determine a threshold level for the local station, and transmit the determined level to other stations in the system. The station also receives similar information from other stations in the system and determines, based at least in part on the information received and the local determined threshold level, an optimal carrier sensing threshold level.

Abstract: A system and method for improved cache performance is disclosed. In one embodiment, a processor with a cache having a dirty cache line subject to eviction may send the dirty cache line to an available replacement block in another processor's cache. In one embodiment, an available replacement block may contain a cache line in an invalid state. In another embodiment, an available replacement block may contain a cache line in an invalid state or in a shared state. Multiple transfers of the dirty cache line to more than one processor's cache may be inhibited using a set of accept signals and backoff signals. These accept signals may be combined to inhibit multiple processors from accepting the dirty cache line, as well as to inhibit the system memory from accepting the dirty cache line.

Abstract: A method for adjusting the voltage and frequency to minimize power dissipation in a processor. The method of one embodiment comprises determining a power consumption value. The power consumption value is evaluated to obtain a new operating point. The new operating point is compared with a present operating point. A frequency setting and a voltage setting are adjusted to correspond to the new operating point if the new operating point is different from the present operating point.

Abstract: A network route tracing system traces a path through a network and identifiesnetwork components and communications links affected by the path. According to one embodiment of the present invention, a route is traced between two hosts in a network. The network is represented as a logical tree having a plurality of nodes. Each one of the nodes corresponds to a component in the network and each non-root node has a parent node. Two nodes are identified in the logical tree. A first node corresponds to a first host and a second node corresponding to a second host. If one of the two nodes exists at a lower level of the logical tree, then a first path is traced from the first node at the lower level to the parent node at a higher level until the parent node is at a same level of the logical tree as the second node. The first path is further traced up the logical tree from the parent node and a second path is traced up the logical tree from the second node until the first path and the second path meet at a same node.

Abstract: The operating rate of an electronic system is maximized without exceeding a thermal constraint, such as a maximum junction temperature of an integrated circuit (IC) or other portion of the electronic system. An operating parameter of the system that controls the thermal output of the system is calculated for an upcoming time period based upon the previously measured thermal performance relationship to the operating parameter level. If the predicted thermal performance will exceed a maximum allowable level of the thermal constraint, then the operating parameter is reduced by an amount calculated to keep the thermal constraint at a level just below the maximum allowable level, thus resulting in an optimal control approach to maximizing the system performance while not exceeding the thermal constraint.

Abstract: An embodiment of the present invention provides a method of pre-allocating and communicating IP address information during wireless communication by an access point, comprising pre-caching by said AP a predetermined number of IP addresses from a backend Dynamic Host Configuration Protocol (DHCP) server. An embodiment may further comprise providing by said AP an IP subnet roaming information element that provides the IP Address that a wireless station (STA) will be obtaining if a wireless station (STA) roams to a particular AP and providing by said AP an IP subnet roaming information element that provides an IP subnet mask that determines the network address and host address portion of the IP addresses and providing by said AP provides an IP subnet roaming information element that provides that provides a Default gateway router address.