Intel Patents
Intel Corporation designs and manufactures microprocessors and chipsets for computing and communications equipment manufacturers. Its products may be found in desktops, servers, tablets, smartphones and other devices.
Intel Patents by Type- Intel Patents Granted: Intel patents that have been granted by the United States Patent and Trademark Office (USPTO).
- Intel Patent Applications: Intel patent applications that are pending before the United States Patent and Trademark Office (USPTO).
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Patent number: 6931598Abstract: An arrangement is provided for dynamic web list display. A view page is displayed at a client site. The view page hosts a plug-in and supplies the plug-in a link to a filler page on a server. The filler page provides list content with specified content structure. The plug-in downloads the filler page from the server site and renders the list content according to the content structure specified by the filler page.Type: GrantFiled: March 30, 2001Date of Patent: August 16, 2005Assignee: Intel CorporationInventors: Stephen H. Price, Tyler Packer, Michael G. Collins, Jason V. Butterfield
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Patent number: 6931505Abstract: One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at least one memory module by way of a point-to-point interface. The data cache and associated logic are located in one or more buffer components on each of the memory modules. The memory controller communicates with the memory module via a variety of commands. Included in these commands are an activate command and a cache fetch command. A command is delivered from the memory controller to the memory modules over four transfer periods. The activate command and the cache fetch command have formats that differ only in the information delivered in the fourth transfer period. A read command and a read and preload command similarly differ only in the information delivered over the fourth transfer period.Type: GrantFiled: December 31, 2001Date of Patent: August 16, 2005Assignee: Intel CorporationInventor: Howard S. David
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Patent number: 6931490Abstract: Set address correlation correlates between addresses belonging to a common address set. Addresses are grouped into address sets and correlations are created between addresses by set. The correlations are used to predict future addresses based on current addresses.Type: GrantFiled: December 15, 2000Date of Patent: August 16, 2005Assignee: Intel CorporationInventors: Wayne A. Wong, Christopher B. Wilkerson
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Patent number: 6931498Abstract: A single status register, capable of providing status for simultaneous read-while-write operation on a flash memory array is described. The status of the memory array is reported to the user based on two partitions. A microcontroller is used to traffic the status register to memory array communication.Type: GrantFiled: April 3, 2001Date of Patent: August 16, 2005Assignee: Intel CorporationInventors: Sanjay S. Talreja, Jason Panavich, Ramkarthik Ganesan, Terry L. Kendall
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Publication number: 20050177617Abstract: Conflict resolution during data synchronization may be improved by sending an update version along with a synchronization request to a user having previously received a different update version from the user.Type: ApplicationFiled: December 23, 2003Publication date: August 11, 2005Applicant: Intel CorporationInventors: Rajesh Banginwar, Jonathan Gitlin
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Publication number: 20050177605Abstract: Efficiency of computation of logarithmic and exponential functions may be improved using multiplication by pre-computed coefficients to obtain intermediate products.Type: ApplicationFiled: February 10, 2004Publication date: August 11, 2005Applicant: Intel CorporationInventor: Raghavan Sudhakar
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Publication number: 20050175306Abstract: Optical waveguides with integrated collimating lenses and/or reflectors or mirrors are disclosed. The waveguides can include a convex collimating lens disposed at an end of the core. An integrated reflecting device may be inserted into the core so that at least a portion of the signal is directed upward through a convex collimating lens disposed above the upper cladding and core for power monitoring. An additional integrated reflecting device may be incorporated beyond a distal end of the core of the waveguide for power monitoring. The lenses and reflective devices or mirrors are made using reflow techniques and therefore do not require the use of separate, prefabricated components.Type: ApplicationFiled: April 7, 2005Publication date: August 11, 2005Applicant: INTEL CORPORATIONInventors: Gabel Chong, Hiroaki Fukoto, Xuejun Ying
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Patent number: 6928572Abstract: A clock delay circuit has a plurality of outputs to provide a sequence of clock signals that togther constitute a multistage clock. The circuit further has a delay adjustment input to adjust the timing of the clock signals for at least one of the outputs relative to the clock signals at another of the outputs. In an embodiment, the circuit has a plurality of these delay adjustment inputs. In a further embodiment, the circuit has a plurality of buffer components to delay the clock signals.Type: GrantFiled: June 29, 2001Date of Patent: August 9, 2005Assignee: Intel CorporationInventors: Thomas D. Fletcher, Giao Pham
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Patent number: 6928548Abstract: In one embodiment, a digitally signed image is embodied in a memory component such as a non-volatile memory. The digitally signed image comprises a post-relocation image and a digital signature. The post-relocation image is an image of a software module altered by a symmetrical relocation function by loading of the image into the memory component. The digital signature is based on the image so that it can be used to analyze data integrity.Type: GrantFiled: September 29, 2000Date of Patent: August 9, 2005Assignee: Intel CorporationInventors: Robert P. Hale, Andrew J. Fish
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Patent number: 6928624Abstract: A method includes creating a first window to receive video which at least partially overlaps a second window on a region of overlap of the display. Pixels of the first window are set to a chroma color. Background pixels of the second window in the region of overlap are also set to the chroma color, The second window is configured to draw after the first window.Type: GrantFiled: March 6, 2000Date of Patent: August 9, 2005Assignee: Intel CorporationInventor: Jim B. Estipona
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Patent number: 6928605Abstract: How a first result of a first operation compares to a second result of a second operation is identified. The identification may be performed without producing the first result or the second result. The first result or the second result may be selected in response to the identification, and the first operation or the second operation may be performed in response to the selection to produce the selected result. Alternatively, the first operation may be performed to produce the first result and the second operation may be performed to produce the second result. The produced first result or the produced second result may be selected in response to the identification.Type: GrantFiled: March 29, 2002Date of Patent: August 9, 2005Assignee: Intel CorporationInventor: Gad S. Sheaffer
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Patent number: 6928503Abstract: A bus system comprises a bus, a first bus device on the bus at a first virtual address and at a first physical address on the bus, and a second bus device on the bus at a second virtual address and a second physical address. The bus system further comprises a map of the first and second virtual addresses to the first and second physical addresses, respectively, encoded on a program storage medium. The map is accessible over the bus. The first and second virtual addresses may each be, for example, a guaranteed unique identifier (GUID).Type: GrantFiled: June 10, 1998Date of Patent: August 9, 2005Assignee: Intel CorporationInventor: Ronald L. Mosgrove
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Patent number: 6927497Abstract: A semiconducting package includes a first capsule, a second capsule and an adhesive within a recess in a surface of the first capsule that secures the first capsule to the second capsule.Type: GrantFiled: August 22, 2002Date of Patent: August 9, 2005Assignee: Intel CorporationInventor: John G. Meyers
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Patent number: 6928456Abstract: A method of directly reading addresses from flash memory using an object tracking table is described. Some applications such as K-Java typically require their data to be stored contiguous in memory. In order to achieve contiguous memory space, free memory is compressed during reclaim. The data compression may alter the address locations within the application files. The object tracking table helps enable direct flash access to modify and update flash object data.Type: GrantFiled: March 6, 2001Date of Patent: August 9, 2005Assignee: Intel CorporationInventors: Akila Sadhasivan, Richard P. Garner
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Patent number: 6927496Abstract: An embodiment of the present invention is a technique to distribute clock. At least a metal layer is formed to have a standing-wave structure to distribute a clock signal to receiver end points from a clock source such that the receiver end points are substantially electrically equivalent with respect to the clock source. The metal layer is embedded in dielectric layers made of thick film using a wafer-level thick film (WLTF) process.Type: GrantFiled: September 30, 2003Date of Patent: August 9, 2005Assignee: Intel CorporationInventors: Henning Braunisch, Anna M. George, Steven N. Towle
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Patent number: 6928582Abstract: A system and method for exception handling includes executing a first instruction. The first instruction then returns an exception. A program counter is used to determine the location of a second instruction. The second instruction includes a pointer to at least one exception handler.Type: GrantFiled: January 4, 2002Date of Patent: August 9, 2005Assignee: Intel CorporationInventors: Ali-Reza Adl-Tabatabai, Guei-Yuan Lueh, Tatiana Shpeisman
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Patent number: 6928055Abstract: Briefly, in accordance with one embodiment of the invention, a system includes: a network interface unit (NIU). The network interface unit (NIU) is adapted to monitor bandwidth utilization of the netrwork interface unit and adjust the minimum interval for the transmission of a flow control packet, based, at least in part, on the bandwidth utilization determination. Briefly, in accordance with another embodiment of the invention, an apparatus includes at least one integrated circuit. The integrated circuit includes the capability, either alone or in combination with other integrated circuits, to monitor the receive rate utilization of a network interface unit and adjust the minimum interval for the transmission of a flow control frame, based, at least in part, on the receive rate utilization determined.Type: GrantFiled: August 5, 2003Date of Patent: August 9, 2005Assignee: Intel CorporationInventor: Jie Ni
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Patent number: 6926070Abstract: A cooling system is provided with a heat exchanger that has a thermally conductive tube over-molded with a plurality of thermally conductive fins. To form the heat exchanger, a thermally conductive tube is provided. Insert molding, over molding or injection molding is utilized to incorporate thermally conductive fins with the thermally conductive tubes. The molding process may also simultaneously create any required features, such as mounting features and fittings for tubing to be connected to the heat exchanger.Type: GrantFiled: March 22, 2002Date of Patent: August 9, 2005Assignee: Intel CorporationInventors: Kurt A. Jenkins, John G. Oldendorf, Peter Davison
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Patent number: 6928051Abstract: Embodiments of application based bandwidth limiting proxy servers are described.Type: GrantFiled: December 18, 2000Date of Patent: August 9, 2005Assignee: Intel CorporationInventors: Alan B. Butt, David A. Eatough, Tony N. Sarra
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Patent number: 6928101Abstract: Binary and Quadrature Feher's Modulation (F-Modulation, or FMOD) Transmitter-Receiver systems and circuits exhibit reduced envelope fluctuation and peak radiation, and increased efficiency. A subclass of these systems has a constant envelope. They advantageously provide lower power operation with improved performance including robust BER performance, and compatibility with both linearly and nonlinearly amplified narrow spectrum, and without disadvantages of conventional BPSK, DBPSK QPSK and pi/4-QPSK. Feher's BPSK (FBPSK) is an improved efficiency transmitter which is compatible with conventional BPSK receivers. FBPSK modems are based on using quadrature structure where Q-channel data is inserted in quadrature with I-channel data for certain applications. The Q-channel data may be “offset” from the I-channel data by an amount selectable between zero and a specified time. Further improvement in the spectrum is attained using correlation between I and Q channels. FBPSK modem is shown to meet the IEEE 802.Type: GrantFiled: June 26, 2002Date of Patent: August 9, 2005Assignee: Intel CorporationInventor: Kamilo Feher
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Patent number: 6927146Abstract: The present invention discloses a method including: providing a silicon wafer; forming a buried oxide (BOX) in the silicon wafer below a silicon body; and reducing a thickness of the silicon body by chemical thinning.Type: GrantFiled: June 17, 2003Date of Patent: August 9, 2005Assignee: Intel CorporationInventors: Justin K. Brask, Mohamed A. Shaheen, Ruitao Zhang
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Patent number: 6928426Abstract: Techniques to manage a file are described. An apparatus may comprise a file system interface for a client to receive a request for a file having a file name. The client may generate a unique identifier for the file name in response to the request using a stream cone messaging system, with the unique identifier to represent the file name and comprising a fewer number of bits than the file name. An interconnect system connected to the client may communicate the unique identifier and file name to the server. Other embodiments are described and claimed.Type: GrantFiled: December 30, 2000Date of Patent: August 9, 2005Assignee: Intel CorporationInventor: Steven C. Dake
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Patent number: 6928494Abstract: A method and apparatus for communicating commands and/or data between two different time domains. In one embodiment, multiple memory commands are placed into one or more FIFOs in a manner that specifies the delays that must take place between execution of the different commands. Along with the commands, delay information is placed into the FIFOs, specifying the number of clock cycles, or other form of time delay, that must elapse between execution of a command and execution of a subsequent command. This delay information is used to delay the execution of the subsequent command for the specified time period, while minimizing or eliminating any excess delays. Cue information can also be placed into the FIFOs with the commands to specify which commands must wait for other commands before beginning execution. The delay and cue information is determined and created in the time domain that initiates the transfers. The delays and cueing are executed in the other time domain.Type: GrantFiled: March 29, 2000Date of Patent: August 9, 2005Assignee: Intel CorporationInventors: Andrew M. Volk, Michael W. Williams, David J. McDonnell
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Patent number: 6928209Abstract: An optical add/drop multiplexer may be formed using ring resonators. In some embodiments, ring resonators may be used instead of Bragg gratings in a Mach-Zehnder interferometer configuration. One or more wavelengths may be added or dropped or a band pass of wavelengths may be added or dropped in a wavelength division multiplexed system.Type: GrantFiled: February 15, 2003Date of Patent: August 9, 2005Assignee: Intel CorporationInventors: Jun Su, Yi Ding
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Patent number: 6928200Abstract: A method and apparatus that includes a first waveguide segment that differentially changes the amplitude of the light relative to a first polarization orientation, a thickness of oriented liquid crystal or other birefringent material sufficient to delay one polarization component one-half wavelength relative to another, and a second waveguide segment that also differentially changes the amplitude of the light based on the polarization orientation. Also, an apparatus that includes a thin polarization converter that includes a thin first substrate that is substantially transparent to a wavelength of light, and a birefringent material deposited on one or more surfaces of the first substrate and oriented such that the polarization converter forms a half-wavelength birefringent plate for the light. Also, an apparatus having a first substrate surface, a second substrate surface, and a liquid crystal material between the first and second substrate surfaces to form a polarization converter.Type: GrantFiled: October 7, 2002Date of Patent: August 9, 2005Assignee: Intel CorporationInventors: Nagesh K. Vodrahalli, Achintya K. Bhowmik, Connie C. Liu, Takaharu Fujiyama, Kenji Takahashi, Biswajit Sur
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Patent number: 6927377Abstract: Prior art wavelength lockers used in tunable laser systems can provide information to ensure that the laser is locked onto a channel, but do not provide information as to which specific channel the laser is locked onto. Embodiments of the present invention include a wavelength locking channel monitor that provides a servo-locking error signal and a channel-identifying signal to allow a tunable laser to be updated to lock to the proper channel. Embodiments of the present invention include wavelength-dependent periodic and/or monotonic filters, which provide monotonically variable finesse and a monotonically variable transmission. Embodiments of the present invention also extracts amplitudes, phases, frequency, and/or modulation depths from a dither introduced in an incident light beam to determine the laser channel and the laser mode within that channel.Type: GrantFiled: March 31, 2003Date of Patent: August 9, 2005Assignee: Intel CorporationInventor: William B. Chapman
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Patent number: 6927346Abstract: Apparatus and methods for interconnecting a SMT component interconnect to a via-in-pad (VIP) interconnect. A first reflowable material is deposited on the VIP bond pad. A sphere having a higher melt temperature than the reflow temperature of the first interconnect material is deposited on the first interconnect material. A first reflow process is performed to interconnect the sphere and the VIP bond pad while the sphere remains solid, and the first reflowable material preventing the first interconnect material from migrating into the via-in-pad.Type: GrantFiled: December 20, 2002Date of Patent: August 9, 2005Assignee: Intel CorporationInventors: Carolyn R. McCormick, Terrance J. Dishongh
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Patent number: 6927082Abstract: Defective contact plug fills can be detected by applying an etching solution, which in some embodiments preferentially etches in the <111> direction. The etching solution is some embodiments may also produce a characteristic type of undercutting underneath the contact plug fill. Contact plug fills with defects in them have undercutting underneath as a result of the etchant exposure, while defective contact plug fills have no such undercutting. The contact plug fills that are now undercut by etching exposure are unable to dissipate surface charge or surface applied potential and can be detected using voltage contrast methods or conventional electrical testing techniques, for example.Type: GrantFiled: March 10, 2004Date of Patent: August 9, 2005Assignee: Intel CorporationInventors: Swaminathan Sivakumar, Oleg Golonzka, Timothy F. Crimmins
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Patent number: 6928599Abstract: Decoding an encoded block of data is accomplished by partitioning the block into a first and a second sub-block and performing forward and backward iterative calculations on the sub-blocks in separate processes. Based on results of the iterative calculations an output matrix may be calculated for each sub-block. The outputs may be combined.Type: GrantFiled: December 5, 2001Date of Patent: August 9, 2005Assignee: Intel CorporationInventors: Ophir Edlis, Sharon Levy, Erez Schwartz, Gadi Mazuz, David Deitcher, Noam Mizrahi
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Patent number: 6928076Abstract: One aspect of the invention relates to a messaging communication scheme for controlling, configuring, monitoring and communicating with a signal processor within a Voice Over Packet (VoP) subsystem without knowledge of the specific architecture of the signal processor. The messaging communication scheme may feature the transmission of control messages between a signal processor and a host processor. Each control message comprises a message header portion and a control header portion. The control header portion includes at least a catalog parameter that indicates a selected grouping of control messages and a code parameter that indicates a selected operation of the selected grouping.Type: GrantFiled: September 21, 2001Date of Patent: August 9, 2005Assignee: Intel CorporationInventors: Manoj Mehta, Saurin Shah, Dianne Steiger, Chris Lawton, Anurag Bist
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Patent number: 6928208Abstract: A set of three gratings may be operated in a vernier loop fashion to select a particular wavelength from a wavelength division multiplexed system. As a result, an optical add/drop multiplexer may be provided that can be tuned to select a desired wavelength. In one embodiment, the tuning may be done thermo-optically.Type: GrantFiled: June 30, 2003Date of Patent: August 9, 2005Assignee: Intel CorporationInventors: David A.G. Deacon, Steven J. Madden, Jorg Hubner
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Patent number: 6927156Abstract: A method and apparatus for making pad structures suitable for wirebonding and, optionally, also for solder-ball connections. Some embodiments include an electronics chip having a substrate with circuitry, a compliant electrically insulating layer deposited on at least a portion of the substrate, and an electrical connection pad, the pad having an electrical connection to the circuitry through an aperture in the insulating layer and a peripheral bonding zone region extending over the insulating layer. In some embodiments, the bonding zone is exclusively over the insulating layer outside of the aperture. In some embodiments, the pads are suitable for both solder-ball and wirebond connections. By making a wirebond connection to an area of a pad over the compliant insulating layer, the underlying circuitry is protected from ultrasonic energy of the bonding process.Type: GrantFiled: June 18, 2003Date of Patent: August 9, 2005Assignee: Intel CorporationInventor: Ranjan J. Mathew
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Patent number: 6928266Abstract: A wireless device is provided with a wireless transceiver to transmit and receive signals in accordance with a first protocol to and from network devices of a first wireless network, and a controller manager to control operation of the wireless transceiver. The wireless device is further provided with a wireless receiver to receive signals transmitted in accordance with a second protocol by network devices of a second wireless network, and the controller manager is equipped to control operation of the wireless transceiver based at least in part on at least one signaling characteristic of the received signals from network devices of the second wireless network, to reduce interference with proximately located ones of the network devices of the second wireless network. In various embodiments, the controller manager suspends operation of the wireless transceiver whenever interference is predicted.Type: GrantFiled: November 12, 1999Date of Patent: August 9, 2005Assignee: Intel CorporationInventors: Ron Nevo, Ephraim Zehavi, Brett A. Monello
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Patent number: 6928161Abstract: An echo cancellation unit includes a model store to store a current echo model from an adaptive filter when a real-time error occurs. The real-time error is detected by monitoring a convergence metric. In some embodiments, the convergence metric is echo return loss enhancement (ERLE). When a real-time error occurs, the current echo model is saved, and the adaptive filter is reset such that it will begin converging from the origin. As a new model emerges in the adaptive filter, it is compared to the saved model in the model store at several time lags. If a match is found, the emerging model is replaced with the saved model at the appropriate time lag. The result is faster convergence of the adaptive filter than if the adaptive filter were left to converge on its own.Type: GrantFiled: May 31, 2000Date of Patent: August 9, 2005Assignee: Intel CorporationInventor: David L. Graumann
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Patent number: 6927097Abstract: An underfill material is applied to an electronic component, such as a die, integrated circuit (IC) package, or printed circuit board, prior to mounting of the component upon another packaging element. In an embodiment, the component may be a singulated IC package. Strips of underfill material may be separated from a supply reel and applied to the edges of the IC package. Trays may convey the components to and from automated underfill attach equipment. Assembly methods, as well as application of the package to an electronic assembly and to an electronic system, are also described.Type: GrantFiled: March 27, 2003Date of Patent: August 9, 2005Assignee: Intel CorporationInventor: Stewart Dunlap
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Patent number: 6927140Abstract: A method for forming a base of a bipolar transistor. A narrow base is formed using a flash of boron doping gas in a reaction chamber to create a narrow base with high boron concentration. This method allows for reliable formation of a base with high boron concentration while maintaining manageability in controlling deposition of other materials in a substrate.Type: GrantFiled: August 21, 2002Date of Patent: August 9, 2005Assignee: Intel CorporationInventors: Ravindra Soman, Anand Murthy
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Patent number: 6926955Abstract: According to one aspect of the invention, a structure and method for providing improved thermal conductivity of a thermal interface material (TIM) made of phase changed polymer matrix and a fusible filler material is disclosed. The TIM may also have a non-fusible filler material and a percentage of a non-phase change polymer added to the phase change polymer matrix. The TIM, used to mate and conduct heat between two or more components, can be highly filled systems in a polymeric matrix where the fillers are thermally more conductive than the polymer matrix.Type: GrantFiled: February 8, 2002Date of Patent: August 9, 2005Assignee: Intel CorporationInventors: Saikumar Jayaraman, Paul A. Koning, Ashay Dani
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Patent number: 6928216Abstract: A lithographic process is used to place a marking on a waveguide to indicate optical channels within the waveguide. A photonic component is positioned against the waveguide based on the markings and adjusted until aligned.Type: GrantFiled: September 26, 2003Date of Patent: August 9, 2005Assignee: Intel CorporationInventors: Venkatesan Murali, Rama K. Shukla
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Patent number: 6927638Abstract: Some embodiments provide a charge pump to output a first control signal and a second control signal based on a frequency of an oscillating signal and a reference frequency, a switch capacitor circuit to generate a first output capacitance based on the first control signal, a main loop circuit to generate an output signal based on the second control signal, and an oscillating circuit to generate the oscillating signal, the frequency of the oscillating signal based at least on the first output capacitance and the output signal.Type: GrantFiled: September 29, 2003Date of Patent: August 9, 2005Assignee: Intel CorporationInventor: Robert C. Glenn
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Patent number: 6928647Abstract: The present invention provides a method and apparatus for controlling a processing priority assigned alternately to a first thread and a second thread in a multithreaded processor to prevent deadlock and livelock problems between the first thread and the second thread. In one embodiment, the processing priority is initially assigned to the first thread for a first duration. It is then determined whether the first duration has expired in a given processing cycle. If the first duration has expired, the processing priority is assigned to the second thread for a second duration.Type: GrantFiled: February 13, 2003Date of Patent: August 9, 2005Assignee: Intel CorporationInventor: David J. Sager
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Patent number: 6928645Abstract: Speculative pre-computation and multithreading (SP), allows a processor to use spare hardware contexts to spawn speculative threads to very effectively pre-fetch data well in advance of the main thread. The burden of spawning threads may fall on the main thread via basic triggers. The speculative threads may also spawn other speculative threads via chaining triggers.Type: GrantFiled: March 30, 2001Date of Patent: August 9, 2005Assignee: Intel CorporationInventors: Hong Wang, Jamison Collins, John P. Shen, Bryan Black, Perry H. Wang, Edward T. Grochowski, Ralph M. King
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Patent number: 6928593Abstract: A memory component with built-in self test includes a memory array. An input/output interface is coupled to the memory array and has a loopback. A controller is provided to transmit memory array test data to the memory array to store the memory array test data, and to read the memory array test data from the memory array. A compare register is also provided to compare the memory array test data transmitted to the memory array with the memory array test data read from the memory array.Type: GrantFiled: September 18, 2000Date of Patent: August 9, 2005Assignee: Intel CorporationInventors: John Halbert, Randy M. Bonella
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Patent number: 6928080Abstract: Transporting a variable length AAL CPS packet over a non-ATM-specific bus includes determining a variable length AAL CPS packet and transmitting the variable length AAL CPS packet over a non-ATM-specific bus. A first part of the variable length AAL CPS packet is received and a length of the variable length AAL CPS packet is determined and then used to determine synchronization information. Reception of the variable length AAL CPS packet continues, and the synchronization information is used to determine that reception of the variable length AAL CPS packet is complete.Type: GrantFiled: June 28, 2001Date of Patent: August 9, 2005Assignee: Intel CorporationInventor: Allen Peilen Chen
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Patent number: 6928123Abstract: A high-speed transmitter for digital data having a variable data rare, the transmitter comprising a convolutional encoder, adapted to generate, for each group of k input bits in a bitstream, n coded output bits, such that k and n are integers, n equal to or greater than k, and at least one of k and n is variable responsive to the variable data rate of the transmitter; and a modulator, coupled to map the output bits generated by the encoder to a constellation of M symbols for transmission by the transmitter, M an integer, which is variable responsive to the variable data rate of the transmitter; and wherein for a given rate Rs of transmission of the symbols by the transmitter, the variable data rate Rb is given by Rb=Rs*log 2(M)*Rc, wherein Rc is a code rate equal to k/n.Type: GrantFiled: April 12, 2001Date of Patent: August 9, 2005Assignee: Intel CorporationInventor: Ephraim Zehavi
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Patent number: 6928638Abstract: A host system for generating a software built-in self-test engine (SBE) is provided for enabling on-chip generation and application of a re-generative functional test on a complex device such as a microprocessor under test. The host system comprises user directives provided to indicate user desired actions; instruction information provided to define a suite of instructions; and a SBE generation tool arranged to generate a software built-in self-test engine (SBE) based on the user directives, the instruction information and device constraints, for subsequent storage on-board of a complex device such as a microprocessor under test and activation of a re-generative functional test on the complex device under test (DUT).Type: GrantFiled: August 7, 2001Date of Patent: August 9, 2005Assignee: Intel CorporationInventors: Praveen K. Parvathala, Kailasnath Maneparambil, William C. Lindsay, Kamalnayan Jayaraman, Geliang Zhou
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Patent number: 6927757Abstract: Camera driven virtual workspace management is disclosed. A digital camera captures an input video stream comprising images of a surrounding environment limited by a field of view of the camera. The input video stream is processed by a handheld computer coupled to the camera. Parameters that define a partial view of a virtual workspace are redefined based upon motion analysis of the input video stream performed by the handheld computer during the processing.Type: GrantFiled: September 18, 2001Date of Patent: August 9, 2005Assignee: Intel CorporationInventors: Stephen Junkins, Jason E. Plumb, Fernando C. M. Martins
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Patent number: 6928571Abstract: Technique and system for adjusting delays between signals. A number of signals are produced, and delays between the signals are determined. Programmable delay elements are used, each driven by a signal indicative of one of the delays. By delaying each of a number of the signals by different amounts, the signals can be caused to arrive at desired times, e.g., in synchronism with one another.Type: GrantFiled: September 15, 2000Date of Patent: August 9, 2005Assignee: Intel CorporationInventors: Randy M. Bonella, John B. Halbert
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Patent number: 6927180Abstract: By exposing dielectrics to a strong electric field, anisotropic characteristics may be introduced into the dielectric. This may result in the dielectric having different dielectric constants in different directions. As integrated circuits scale, importance of line to line capacitance in one plane increases. Thus, in some embodiments, the dielectric constant of the oriented dielectric may be lower in the plane that controls line to line capacitance.Type: GrantFiled: November 27, 2002Date of Patent: August 9, 2005Assignee: Intel CorporationInventors: Kevin O'Brien, David Gracias
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Patent number: 6928094Abstract: A laser driver circuit to provide a current signal to power a laser device is described. A bias current provided to the laser device may be changed while changes in the output power of a light signal from the laser device is monitored. A slope efficiency associated with the laser device may be determined based upon the changes in the bias current and changes in the output power.Type: GrantFiled: December 16, 2002Date of Patent: August 9, 2005Assignee: Intel CorporationInventors: Bhushan Asuri, Taesub Yoon
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Publication number: 20050168939Abstract: A small water-cooling type electronic component cooling apparatus is provided. The electronic component cooling apparatus comprises a so-called water-cooling heat sink 3, a radiator 7 cooled by an electric fan 5, first and second coolant paths 9, 11 for circulating a coolant between the heat sink 3 and the radiator 7, and an electric pump 13 to supply a moving energy to the coolant. The electric pump 13 is arranged at a position facing the heat-radiating portion of the radiator 7.Type: ApplicationFiled: February 2, 2005Publication date: August 4, 2005Applicants: Sanyo Denki Co., Ltd., Intel CorporationInventors: Masayuki Iijima, Tomoaki Ikeda, Masashi Miyazawa, Kouji Ueno, Paul Gwin, Brian Long, Peter Davison, Rolf Konstad