Abstract: Fin shaping, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure above a substrate. The protruding fin portion has substantially vertical upper sidewalls and outwardly tapered lower sidewalls. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack, and a second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.

Abstract: Embodiments described herein provide techniques to facilitate instruction-based control of memory attributes. One embodiment provides a graphics processor comprising a processing resource, a memory device, a cache coupled with the processing resources and the memory, and circuitry to process a memory access message received from the processing resource. The memory access message enables access to data of the memory device. To process the memory access message, the circuitry is configured to determine one or more cache attributes that indicate whether the data should be read from or stored the cache. The cache attributes may be provided by the memory access message or stored in state data associated with the data to be accessed by the access message.

Abstract: Apparatus and method for stable and short latency sorting.

Abstract: A memory device including a memory array and address lines; and decoder circuitry to apply a first bias to a WL coupled to a memory cell selected for a memory operation, a second bias to a BL coupled to the selected memory cell, and one or more neutral biases to the other BLs and WLs of the memory array; wherein the decoder circuitry comprises a plurality of bias circuits coupled to the address lines, a first bias circuit of the plurality of bias circuits comprising a transistor pair and an additional transistor coupled to an address line of the plurality of address lines, wherein the bias circuit is to apply, to the address line, the first bias through the transistor pair in a first state, the second bias through the transistor pair in a second state, and the neutral bias through the additional transistor in a third state.

Abstract: Methods, apparatus, systems and articles of manufacture for video coding using object metadata are disclosed. An example apparatus includes an object separator to separate input views into layers associated with respective objects to generate object layers for geometry data and texture data of the input views, a pruner to project the first object layer of a first basic view of the at least one basic views against the first object layer of a first additional view of the at least one additional views to generate a first pruned view and a first pruning mask, a patch packer to tag a patch with an object identifier of the first object, the patch corresponding to the first pruning mask, and an atlas generator to generate at least one atlas to include in encoded video data, the atlas including the patch.

Abstract: An Internet of Things (IoT) network includes an IoT device with a communicator to send a communication including egress frame, protocol library builder to determine available protocols, frame analyzer to analyze an ingress frame, and frame builder to build the egress frame from the ingress frame. An IoT network includes an IoT device with network discoverer to identify available parallel communication channels between the IoT device and target device, payload, payload fragmenter/packager to fragment the payload into sub-objects for transmission, and packet communicator to send sub-objects to the target device over parallel communication channels. An IoT network includes a plurality of IoT devices, which each include a communication channel to an upstream device, a network link to another one of the plurality of IoT devices, a hash calculator to identify a neighbor IoT device, and a communicator to send out a message to the neighbor IoT device.

Abstract: Various embodiments herein are directed to set physical downlink shared channel (PDSCH) default beam behavior for single transmission-reception point (TRP), single downlink control information (DCI) multi-TRP and multi-DCI multi-TRP operation, as well as physical downlink control channel (PDCCH) prioritization based on quasi-colocation (QCL) Type-D for multi-panel reception and single panel reception.

Abstract: Example apparatus to perform service failover as disclosed herein are to detect a failure condition associated with execution of a service by a first compute platform, the execution of the service responsive to a first request. Disclosed example apparatus are also to send a second request to a second compute platform to execute the service. Disclosed example apparatus are further to monitor a queue of the first compute platform for a response to the first request, the response to indicate execution of the service by the first compute platform has completed, and when the response is detected in the queue, discard the response from the queue.

Abstract: A disclosed example involves receiving a message with an action to be performed; determining the message type; and based on the message type, performing an action specified in the message.

Abstract: Apparatus and method for bottom-up BVH refit. For example, one embodiment of an apparatus comprises: a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes; traversal hardware logic to traverse one or more rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node unit comprising circuitry and/or logic to perform refit operations on nodes of the hierarchical acceleration data structure, the refit operations to adjust spatial dimensions of one or more of the nodes; and an early termination evaluator to determine whether to proceed with refit operations or to terminate refit operations for a current node based on refit data associated with one or more child nodes of the current node.

Abstract: Methods, systems, and storage media are described for physical-layer cell identifier (PCI) configuration and Mobility Robustness Optimization (MRO). In particular, some embodiments may be directed to fifth-generation self-organizing network (5G SON) solutions such as the management of distributed physical-layer cell identifier (PCI) configuration, centralized PCI configuration, and MRO. Other embodiments may be described and/or claimed.

Abstract: Embodiments may relate to a microelectronic package. The microelectronic package may include a memory die with: a first memory cell at a first layer of the memory die; a second memory cell at a second layer of the memory die; and a via in the memory die that communicatively couples an active die with a package substrate of the microelectronic package. Other embodiments may be described or claimed.

Abstract: Embodiments include apparatuses, methods, and systems for a photonic device including a first optical component, a second optical component, and a third component, where the first optical component or the second optical component is a redundant component of the photonic device. When the first optical component is enabled, the first optical component is to provide a first input to the third component, or to receive a second input from the third component. Similarly, when the second optical component is enabled, the second optical component is to provide the first input to the third component, or to receive the second input from the third component. The first optical component and the second optical component are arranged to perform a same function. Only one of the first optical component or the second optical component is enabled at a time. Other embodiments may also be described and claimed.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

Abstract: Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure on a low density interconnect (LDI) printed circuit board (PCB) according to an LDI fabrication process and forming one or more fine conductive features on the LDI PCB by performing a fine feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fine gap region within the conductive structure. Other embodiments are described and claimed.

Abstract: Gate all around semiconductor devices, such as nanowire or nanoribbon devices, are described that include a low dielectric constant (“low-k”) material disposed between a first nanowire closest to the substrate and the substrate. This configuration enables gate control over all surfaces of the nanowires in a channel region of a semiconductor device via the high-k dielectric material, while also preventing leakage current from the first nanowire into the substrate.

Abstract: A graphics processor can include a processing cluster array including a plurality of processing clusters coupled with the plurality of memory controllers, each processing cluster of the plurality of processing clusters including a plurality of streaming multiprocessors, the processing cluster array configured for partitioning into a plurality of partitions. The plurality of partitions include a first partition including a first plurality of streaming multiprocessors configured to perform operations for a first neural network, The operations for the first neural network are isolated to the first partition. The plurality of partitions also include a second partition including a second plurality of streaming multiprocessors configured to perform operations for a second neural network. The operations for the second neural network are isolated to the second partition and protected from operations performed for the first neural network.

Abstract: Laptop computers with a movable accessory housing are described herein. An example laptop computer incudes a base, a lid moveably coupled to the base, a display carried by the lid, an arm pivotably coupled to the lid, and an accessory housing carried by the arm. The arm is pivotable to move the accessory housing between a first position in which the accessory housing is disposed along a bottom edge of the lid and a second position in which the accessory housing is disposed along a top edge of the lid.

Abstract: Apparatuses, systems and methods associated with a substrate assembly with an encapsulated magnetic feature for an inductor are disclosed herein. In embodiments, a substrate assembly may include a base substrate, a magnetic feature encapsulated within the base substrate, and a coil, wherein a portion of the coil extends through the magnetic feature. Other embodiments may be described and/or claimed.

Abstract: Methods and apparatus to detect proximity of objects to computing devices using near ultrasonic sound waves are disclosed. An example apparatus includes a signal generator to cause a speaker of a computing device to produce a series of pulses. Successive ones of the pulses are spaced at fixed intervals. Ones of the pulses having a central frequency between 18 kHz and 24 kHz. The example apparatus includes an echo profile generator to process noise information sensed by a microphone of the computing device. The noise information includes the pulses and echoes of the pulses reflected off objects in a vicinity of the computing device. The example apparatus further includes an object detection analyzer to determine whether a first object is within an activation region associated with the computing device based on the pulses and the echoes sensed by the microphone.

Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

Abstract: Embodiments include a cooling solution having a first array of fins, where the first array of fins extend vertically from the substrate, and where adjacent individual fins of the first array are separated from each other by a microchannel. A second array of fins extend vertically from the substrate, where a channel region is between the first array of fins and the second array of fins.

Abstract: Techniques are provided for generation of secure video and tamper detection of the secure video. A methodology implementing the techniques according to an embodiment includes selecting a subset of macroblocks from a video frame to be transmitted and calculating a low frequency metric on each of the selected macroblocks. The method also includes performing a hash calculation on the low frequency metrics to generate a frame signature; encrypting the frame signature (using a private key) to generate an encrypted watermark; and modifying pixels of each of the selected macroblocks to generate the secured video frame, the modifications based on bits of the encrypted watermark that are associated with the selected macroblock. The method further includes authenticating a received video frame by comparing a calculated frame signature to an authenticated frame signature, the authenticated frame signature decrypted (using a public key) from an extracted watermark of the received video frame.

Abstract: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.

Abstract: An apparatus to facilitate graphics rendering is disclosed. The apparatus comprises sequencer hardware to operate in a tile mode to render objects, including performing batch formation to generate one or more batches of received objects, performing tile sequencing for each of the objects to compute tile fill intersects for each of the objects and performing a play sequencing of each of the objects.

Abstract: A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.

Abstract: A die interconnect substrate comprises a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate comprises a multilayer substrate structure comprising a substrate interconnect. The bridge die is embedded in the multilayer substrate structure. The substrate interconnect extends from a level above the bridge die to a level below the bridge die. The multilayer substrate structure further comprises an electrically insulating layer comprising a first electrically insulating material. The multilayer substrate structure further comprises an electrically insulating filler structure located laterally between the bridge die and the electrically insulating layer, wherein the electrically insulating filler structure comprises a second electrically insulating material different from the first electrically insulating material.

Abstract: Some demonstrative embodiments include apparatuses, devices, systems and methods of communicating a PPDU including a training field. For example, an Enhanced Directional Multi-Gigabit (DMG) (EDMG) wireless communication station may be configured to determine one or more Orthogonal Frequency Division Multiplexing (OFDM) Training (TRN) sequences in a frequency domain based on a count of one or more 2.16 Gigahertz (GHz) channels in a channel bandwidth for transmission of an EDMG PPDU including a TRN field; generate one or more OFDM TRN waveforms in a time domain based on the one or more OFDM TRN sequences, respectively, and based on an OFDM TRN mapping matrix, which is based on a count of the one or more transmit chains; and transmit an OFDM mode transmission of the EDMG PPDU over the channel bandwidth, the OFDM mode transmission comprising transmission of the TRN field based on the one or more OFDM TRN waveforms.

Abstract: A capacitor is disclosed that includes a first metal layer and a seed layer on the first metal layer. The seed layer includes a polar phase crystalline structure. The capacitor also includes a ferroelectric layer on the seed layer and a second metal layer on the ferroelectric layer.

Abstract: Apparatuses, methods and storage medium associated with traffic sign recognition, are disclosed herein. In some embodiments, an apparatus includes an orchestrator, disposed in a CA/AD vehicle, to receive a classification and a location of a traffic sign, while the CA/AD vehicle is enroute to a destination. In response, the orchestrator query a remote sign locator service or a local database on the CA/AD vehicle for a reference description of the traffic sign, determine whether the classification is correct, and output a result of the determination. The classification of the traffic sign is generated based at least in part on computer vision, and the orchestrator includes an anomaly detector to detect anomalies between the classification and the reference description, and determine whether the classification is correct based at least in part on an amount of anomalies detected. Other embodiments are also described and claimed.

Abstract: Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

Abstract: A packaged device (110) includes a substrate (114) and one or more contacts (118) disposed on a side of the substrate (114). Structures of the packaged device (110) define at least in part a recess region (120) that extends from the side of the substrate (114) and through the substrate (114), where one or more contacts (124) of a second hardware interface are disposed in the recess region (120). The one or more contacts (118) of the first hardware interface enable connection of the packaged device (110) to a printed circuit board. The one or more contacts (124) of the second hardware interface enable connection between one or more IC dies of the packaged device (110) and another IC die (150) that is a component of the packaged device (110) or of a different packaged device.

Abstract: A head-end equipment associated with a communication system configured to interface with an interference group (IG) composed of two or more modems is disclosed. The head-end equipment comprises a memory configured to store a plurality of instructions; and one or more processors configured to retrieve the plurality of instructions from the memory. In some embodiments, the one or more processors, upon execution of the plurality of instructions from the memory, is configured to generate an advanced warning signal to be provided to one or more modems associated with the IG. In some embodiments, the advanced warning signal comprises an information that a select modem, different from the one or more modems, in the IG will be initiating an upstream communication in a select frequency band, as well as information on a start time and a duration of the upstream communication.

Abstract: Systems, apparatuses, methods, and computer-readable media, are provided for indicating beam failure detection (BFD) and/or beam failure recovery (BFR) information for secondary cells (SCells). Disclosed embodiments enable BFD/BFR reporting for SCells with only downlink or with both downlink and uplink to recover from link failure and/or beam failure. Other embodiments may be described and/or claimed.

Abstract: Embodiments are directed to providing a secure address translation service. An embodiment of a system includes a computer-readable memory for storage of data, the computer-readable memory comprising a first memory buffer and a second memory buffer, an attack discovery unit device comprising processing circuitry to perform operations, comprising, receiving a direct memory access (DMA) request from a remote device via a Peripheral Component Interconnect Express (PCIe) link, the direct memory access (DMA) request comprising a host physical address and a header indicating that the target memory address has previously been translated to a host physical address (HPA), and blocking a direct memory access in response to a determination of at least one of that the remote device has not obtained a valid address translation from a translation agent, or that the remote device has not obtained a valid translation for the target memory address from the translation agent.

Abstract: Methods, systems, and storage media are described for Load Balancing Optimization (LBO) and Mobility Robustness Optimization (MRO) for fifth generation (5G) systems. In particular, some embodiments may be directed intra-radio access technology (RAT) energy saving scenarios while other embodiments may be directed to and inter-RAT energy saving scenarios. Other embodiments may be described and/or claimed.

Abstract: Systems and methods may provide for confirming, by a loader module having administrative rights with respect to a computing device, the operability of an activator module on the computing device. Additionally, the activator module may be used to manage an installation status of one or more service agents or software components on the computing device and making them persistent. In one example, confirming the operability of the activator module includes conducting a presence verification and/or authentication of the activator module, wherein a replacement activator module may be downloaded to the computing device if the presence verification and/or authentication is unsuccessful.

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a fan where the fan blades are decoupled from the center shaft. The fan can include a center shaft, a motor coil support, motor coils coupled to the motor coil support, a rotator coupled to the center shaft, and fan blades coupled to the rotator, where rotation of the fan blades is decoupled from the center shaft by the rotator. A blade support can be coupled to the rotator, where the blade support couples the fan blades to the rotator and magnets can be coupled to the blade support. In an example, the rotator can include an inner, an outer race, and bearings.

Abstract: Embodiments of the present disclosure are directed toward probabilistic in-memory computing configurations and arrangements, and configurations of probabilistic bit devices (p-bits) for probabilistic in-memory computing. concept with emerging. A probabilistic in-memory computing device includes an array of p-bits, where each p-bit is disposed at or near horizontal and vertical wires. Each p-bit is a time-varying resistor that has a time-varying resistance, which follows a desired probability distribution. The time-varying resistance of each p-bit represents a weight in a weight matrix of a stochastic neural network. During operation, an input voltage is applied to the horizontal wires to control the current through each p-bit. The currents are accumulated in the vertical wires thereby performing respective multiply-and-accumulative (MAC) operations. Other embodiments may be described and/or claimed.

Abstract: Systems, apparatuses, and methods to establish a mapping between message identifications for messages transmitted on a communication bus and electronic control units transmitting the messages is provided. In particular, retransmission of a low priority message onto the bus is forced such that the retransmitted low priority message overlaps with a higher priority message to determine whether the messages originated from the same ECU.

Abstract: Techniques related to reduction of artifacts in parallel block coding mode selection for video are discussed. Such techniques include, for blocks along a parallel processing split boundary of a video frame, coding mode selection that divides a block into sub-blocks, performs motion estimation for the sub-blocks with skip check disabled and using distortion and coefficient coding cost but exclusive of motion vector coding cost, and evaluates a skip check for the block using the sub-block motion vectors.

Abstract: Systems for providing coverage enhancement for Msg 3 PUSCH and PUCCH carrying the HARQ-ACK for Msg4 of PRACH initial access are described. The gNB provides a 2-bit aggregation factor for transmission of the Msg3 PUSCH in an RAR UL grant field. The PUSCH frequency resource allocation field is limited to 12 bits so that the RAR has an overall number of bits that is the same as an RAR that does not contain the aggregation factor. A default PUSCH TDRA table includes a field to indicate a repetition level for Msg3 PUSCH transmission. For retransmissions, fields in DCI format 0_0 are repurposed to indicate an aggregation factor. Inter-slot frequency hopping may be configured by higher layers. Different PRACH resources are used to indicate UE coverage status.

Abstract: A data-centric network and non-Real-Time (RT) RAN Intelligence Controller (RIC) architecture are described. The data-centric network architecture provides data plane functions (DPFs) that serve as a shared database for control functions, user functions and management functions for data plane resources in a network. The DPFs interact with control plane functions, user plane functions, management plane functions, compute plane functions, network exposure functions, and application functions of the NR network via a service interface. The non-RT RIC provides functions via rApps, manages the rApps, performs conflict mitigation and security functions, monitors machine learning (ML) performance, provides a ML model catalog that contains ML model information, provides interface terminations and stores ML data and Near-RT RIC related information in a database. An ML training host trains and evaluates ML models in the catalog, obtains training and testing data from the database, and retrains and updates the ML models.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to detect attacks in V2X networks. An example apparatus includes a challenge handler to (a) transmit a first challenge packet to a first vehicle to request a transmission of a first response, (b) instruct a second challenge packet to be transmitted to a second vehicle to request a transmission of a second response, (c) increment a first counter when the first response is not obtained, (d) increment a second counter when the second response is not obtained, and (e) after repeating (a)-(d), determine that the first and second vehicles are phantom vehicles associated with an attacker with a half-duplex radio when at least one of the first or second counters satisfy a threshold, and a network interface to instruct a third vehicle associated with the V2X network to ignore future messages from the phantom vehicles based on the determination.

Abstract: Disclosed embodiments relate to systems and methods to skip inconsequential matrix operations. In one example, a processor includes decode circuitry to decode an instruction having fields to specify an opcode and locations of first source, second source, and destination matrices, the opcode indicating that the processor is to multiply each element at row M and column K of the first source matrix with a corresponding element at row K and column N of the second source matrix, and accumulate a resulting product with previous contents of a corresponding element at row M and column N of the destination matrix, the processor to skip multiplications that, based on detected values of corresponding multiplicands, would generate inconsequential results; scheduling circuitry to schedule execution of the instruction; and execution circuitry to execute the instructions as per the opcode.

Abstract: Among other things, some embodiments of the present disclosure are directed to coverage enhancement techniques for the physical uplink control channel (PUCCH). Specifically, the PUCCH may be transmitted from two or more antenna ports of a user equipment (UE) based on configuration information received from a base station. Other embodiments may be disclosed and/or claimed.

Abstract: Systems and methods for tone mapping of high dynamic range (HDR) images for high-quality deep learning based processing are disclosed. In one embodiment, a graphics processor includes a media pipeline to generate media requests for processing images and an execution unit to receive media requests from the media pipeline. The execution unit is configured to compute an auto-exposure scale for an image to effectively tone map the image, to scale the image with the computed auto-exposure scale, and to apply a tone mapping operator including a log function to the image and scaling the log function to generate a tone mapped image.

Abstract: The present disclosure relates generally to techniques for efficiently performing operations associated with artificial intelligence (AI), machine learning (ML), and/or deep learning (DL) applications, such as training and/or interference calculations, using an integrated circuit device. More specifically, the present disclosure relates to an integrated circuit design implemented to perform these operations with low latency and/or a high bandwidth of data. For example, embodiments of a computationally dense digital signal processing (DSP) circuitry, implemented to efficiently perform one or more arithmetic operations (e.g., a dot-product) on an input are disclosed. Moreover, embodiments described herein may relate to layout, design, and data scheduling of a processing element array implemented to compute matrix multiplications (e.g., systolic array multiplication).

Abstract: The disclosed embodiments enable applying production nature to a software signature post-build (or even post-release), where the signature type is determined by the existence of a production-signed intermediate CA certificate—either hosted in the cloud (for pure release immutability), or re-ingested into the package (if certain modification are allowed). This allows a so-called deferred issuance of the product release. Even if the CA certificate is to be reinserted into the package, this modification likely affects only the delivery shell (e.g., installer) and may not require format-specific binary changes of, possibly heterogeneous, artifacts therein.