Abstract: In one example an apparatus comprises receive, in a processing platform, an input request from a remote device comprising a digital signature signing or verify function and determine a selected digital signature scheme for the request based at least in part on a determination of whether the processing platform is to apply a signing function or a verify function to the input request. Other examples may be described.

Abstract: An apparatus may include an accelerator and a processor. The processor may receive an input string targeting a data buffer comprising a plurality of strings. The processor may receive, from the accelerator, a fixed-length data buffer based on the data buffer, respective ones of a plurality of entries of the fixed-length data buffer based on respective ones of the strings. The processor may receive, from the accelerator, a plurality of streams, respective ones of the plurality of streams to comprise a portion of respective entries in the fixed-length data buffer. The processor may generate, based on the input string, a plurality of target portions of the input string. The processor may receive, from the accelerator, indexes of the plurality of streams based on respective target portions of the input string matching respective entries of the plurality of streams. The processor may aggregate the indexes received from the accelerator.

Abstract: This disclosure describes systems, methods, and devices related to security for multi-link operations. A multi-link device (MLD) may establish a first communication link between a first device of the MLD and a first device of a second MLD, and a second communication link between a second device of the MLD and a second device of the second MLD. The MLD may generate a group-addressed message. The MLD may protect the group-addressed message using a first key or a first integrity key. The MLD may protect the group-addressed message using a second key or a second integrity key. The MLD may send, using the first communication link, the group-addressed message protected using the first key or the first integrity key, and may send, using the second communication link, the group-addressed message protected using the second key or the second integrity key.

Abstract: Systems, apparatuses and methods may provide for technology that generates a first compiler output based on input code that includes dynamically typed variable information and generates a second compiler output based on the input code, wherein the second compiler output includes type check code to verify one or more type inferences associated with the first compiler output. The technology may also execute the first compiler output and the second compiler output in parallel via different threads.

Abstract: Embodiments described herein are generally directed to the use of sidecars to perform dynamic Application Programming Interface (API) contract generation and conversion. In an example, a first call by a first microservice to a first API of a second microservice is intercepted by a first sidecar of the first microservice. The first API is of a first API type of multiple API types and is specified by a first contract. An API type of the multiple API types is selected by the first sidecar. Responsive to determining the selected API type differs from the first API type, based on the first contract, a second contract is generated by the first sidecar specifying a second API of the selected API type; and a second sidecar of the second microservice is caused to generate the second API and internally connect the second API to the first API based on the second contract.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of semiconductor fins having a longest dimension along a first direction. Adjacent individual semiconductor fins of the first plurality of semiconductor fins are spaced apart from one another by a first amount in a second direction orthogonal to the first direction. A second plurality of semiconductor fins has a longest dimension along the first direction. Adjacent individual semiconductor fins of the second plurality of semiconductor fins are spaced apart from one another by the first amount in the second direction, and closest semiconductor fins of the first plurality of semiconductor fins and the second plurality of semiconductor fins are spaced apart by a second amount in the second direction.

Abstract: In various aspects, power saving host-modem interactions are described herein. For instance, a host of a communication device includes a host processor that receives, via an interface, information about the reduced activity state of a modem of the communication device including an indication of the RRC state of the modem. It also receives, via the interface, information about a projected expiration of a reduced activity period of the modem including an indication of a time remaining until a next event of the modem. The host processor controls a reduction of an operation of a component of the communication device during the reduced activity period of the modem, based on the indication of the RRC state of the modem and the indication of the time remaining until the next event of the modem. The reduced activity state of the modem corresponding to the reduced activity period of the modem.

Abstract: An apparatus comprising an interface to receive an identification of a function to be executed; and a scheduling engine comprising circuitry, the scheduling engine to select a candidate compute element from a plurality of candidate compute elements based on a combined burden, the combined burden based on an estimated burden to execute the function by the candidate compute element and an estimated burden of data movement over at least one interconnect identified for the candidate compute element.

Abstract: Apparatus and method for a hierarchical beam tracer.

Abstract: An apparatus to facilitate partially-frozen neural networks for efficient computer vision systems is disclosed. The apparatus includes a frozen core to store fixed weights of a machine learning model, one or more trainable cores coupled to the frozen core, the one or more trainable cores comprising multipliers for trainable weights of the machine learning model, and wherein the alpha blending layer includes a trainable alpha blending parameter, and wherein the trainable alpha blending parameter is a function of a trainable parameter, a sigmoid function, and outputs of frozen and trainable blocks in a preceding layer of the machine learning model.

Abstract: Millimeter-wave (mmWave) and sub-mmWave technology, apparatuses, and methods that relate to receivers for wireless communications are described. The various aspects include an apparatus of a communication device including an antenna array and switching circuitry coupled to each antenna of the antenna array. The switching circuitry is configured to switch at a rate based on the center frequency of incoming communications on each respective antenna to generate at least two antenna patterns and provide the at least two antenna patterns to processing circuitry for decoding.

Abstract: A second-level thermal interface material (TIM2) that is to couple to a system-level thermal solution is applied to an integrated circuit (IC) assembly comprising an IC die and an assembly substrate prior to the assembly substrate being joined to a host component at the system-level. Challenges associated with TIM2 application may therefore be addressed at a first level of IC die integration, simplifying subsequent assembly and better controlling thermal coupling to a subsequently applied thermal solution. Where a first-level IC assembly includes a stiffener, the TIM may be affixed to the stiffener through an adhesive bond or a fusion bond. After the IC assembly including the TIM is soldered to the host board, a thermal solution may be placed in contact with the TIM. With early application of a solder TIM, a solder TIM may be reflowed upon the IC die multiple times.

Abstract: Techniques related to embedding a 3D object model within a 3D scene are discussed. Such techniques include determining two or more object mask images for two or more corresponding cameras trained on the 3D scene, projecting 3D points from the 3D object model to the image planes of the two or more cameras, and determining a position and orientation of the 3D object model in the scene using the object mask images and the projected 3D points.

Abstract: System and techniques for enhanced electronic navigation maps for a vehicle are described herein. A set of map tiles may be received at a vehicle component from a remote entity. Sensor derived data that has a locality corresponding to a map tile in the set of map tiles may be obtained. A field-programmable gate array of the vehicle may then be invoked to combine the sensor derived data and the map tile to create a modified map tile. The modified map tile may be communicated to a control system of the vehicle.

Abstract: Embodiments described herein are generally directed to intelligent management of microservices failover. In an example, responsive to an uncorrectable hardware error associated with a processing resource of a platform on which a task of a service is being performed by a primary microservice, a failover trigger is received by a failover service. A secondary microservice is identified by the failover service that is operating in lockstep mode with the primary microservice. The secondary microservice is caused by the failover service to takeover performance of the task in non-lockstep mode based on failover metadata persisted by the primary microservice. The primary microservice is caused by the failover service to be taken offline.

Abstract: Stacked die semiconductor packages may include a spacer die disposed between stacked dies in the semiconductor package and the semiconductor package substrate. The spacer die translates thermally induced stresses on the solder connections between the substrate and an underlying member, such as a printed circuit board, from electrical structures communicably or conductively coupling the semiconductor package substrate to the underlying structure to mechanical structures that physically couple the semiconductor package to the underlying structure. The footprint area of the spacer die is greater than the sum of the footprint areas of the individual stacked dies in the semiconductor package and less than or equal to the footprint area of the semiconductor package substrate. The spacer die may have nay physical configuration, thickness, shape, or geometry. The spacer die may have a coefficient of thermal expansion similar to that of the lowermost semiconductor die in the die stack.

Abstract: Systems, apparatuses and methods may provide for controlling one or more end effectors by generating a semantic labelled image based on image data, wherein the semantic labelled image is to identify a shape of an object and a semantic label of the object, associating a first set of actions with the object, and generating a plan based on an intersection of the first set of actions and a second set of actions to satisfy a command from a user through actuation of one or more end effectors, wherein the second set of actions are to be associated with the command.

Abstract: Techniques related to training and implementing convolutional neural networks for object recognition are discussed. Such techniques may include applying, at a first convolutional layer of the convolutional neural network, 3D filters of different spatial sizes to an 3D input image segment to generate multi-scale feature maps such that each feature map has a pathway to fully connected layers of the convolutional neural network, which generate object recognition data corresponding to the 3D input image segment.

Abstract: Described herein are integrated circuit (IC) structures, devices, and methods associated with device layer interconnects. For example, an IC die may include a device layer including a transistor array along a semiconductor fin, and a device layer interconnect in the transistor array, wherein the device layer interconnect is in electrical contact with multiple different source/drain regions of the transistor array.

Abstract: Various systems and methods for providing a vehicle control system are described herein. A system for managing a vehicle comprises: a vehicle control system of a vehicle having access to a network, including: a communication module to interface with at least one of: a mobile device, the vehicle, and environmental sensors coupled to the vehicle; and a configuration module to identify a mitigation operation to be taken when predetermined factors exist; wherein the vehicle control system is to identify a potential obstacle in a travel route of the vehicle and initiate a mitigation operation at the vehicle.

Abstract: Microelectronic devices, assemblies, and systems include a microelectronic die and composite material to conduct heat from the microelectronic die such that the composite material includes polymer chains chemically bonded to fill particles having a hexagonal lattice of carbon atoms such as graphene sheet fill particles and/or carbon nanotube fill particles.

Abstract: The present disclosure is directed to an electrostatic charge measurement tool and dedicated system having a probe configured to scan the surface of a target, and methods for taking the electrostatic charge measurements. In an aspect, the probe is a non-contact electrostatic probe that may be moveable across the surface of the target and be adjustable in its height from the surface of the target. In another aspect, the target is an electrostatic chuck or semiconductor wafer. In a further aspect, the electrostatic charge measurement system may perform insitu measurement of targets without removing them from their working environment.

Abstract: Technologies for providing dynamic selection of edge and local accelerator resources includes a device having circuitry to identify a function of an application to be accelerated, determine one or more properties of an accelerator resource available at the edge of a network where the device is located, and determine one or more properties of an accelerator resource available in the device. Additionally, the circuitry is to determine a set of acceleration selection factors associated with the function, wherein the acceleration factors are indicative of one or more objectives to be satisfied in the acceleration of the function. Further, the circuitry is to select, as a function of the one or more properties of the accelerator resource available at the edge, the one or more properties of the accelerator resource available in the device, and the acceleration selection factors, one or more of the accelerator resources to accelerate the function.

Abstract: Systems, articles and methods to provide lens shading color correction using block matching are disclosed. Example processor systems disclosed herein are to process at least one cluster of blocks of an image to determine at least one modification parameter, modify the first shade correction data based on the at least one modification parameter to determine second shade correction data, and correct a lens shade effect associated with the image based on the second shade correction data.

Abstract: A transistor is disclosed. The transistor includes a substrate, a superlattice structure that includes a plurality of heterojunction channels, and a gate that extends to one of the plurality of heterojunction channels. The transistor also includes a source adjacent a first side of the superlattice structure and a drain adjacent a second side of the superlattice structure.

Abstract: A coreless semiconductor package comprises a plurality of horizontal layers of dielectric material. A magnetic inductor is situated at least partly in a first group of the plurality of layers. A plated laser stop is formed to protect the magnetic inductor against subsequent acidic processes. An EMIB is situated above the magnetic inductor within a second group of the plurality of layers. Vias and interconnections are configured within the horizontal layers to connect a die of the EMIB to other circuitry. A first level interconnect is formed on the top side of the package to connect to the interconnections. BGA pockets and BGA pads are formed on the bottom side of the package. In a second embodiment a polymer film is used as additional protection against subsequent acidic processes. The magnetic inductor comprises a plurality of copper traces encapsulated in magnetic material.

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region.

Abstract: An apparatus and method are described for performing an early depth test on graphics data. For example, one embodiment of a graphics processing apparatus comprises: early depth test circuitry to perform an early depth test on blocks of pixels to determine whether all pixels in the block of pixels can be resolved by the early depth test; a plurality of execution circuits to execute pixel shading operations on the blocks of pixels; and a scheduler circuit to schedule the blocks of pixels for the pixel shading operations, the scheduler circuit to prioritize the blocks of pixels in accordance with the determination as to whether all pixels in the block of pixels can be resolved by the early depth test.

Abstract: This disclosure describes systems, methods, and devices related to null data packet (NDP) frame format. A device may cause to send a null data packet announcement (NDPA) frame to a responding station device (RSTA). The device may cause to send a first sounding NDP frame comprising one or more fields formatted to support 2.4 gigahertz (GHz) and 5 GHz bands in a non-trigger-based ranging measurement with the RSTA. The device may identify after a passage of a short inter-frame space (SIFS) time a second NDP frame received from the RSTA. The device may identify a location measurement report frame from the RSTA.

Abstract: The application provides a method, including: generating a Physical Layer (PHY) Protocol Data Unit (PPDU) comprising both information for one or more first-generation stations (R1 STAs) and information for one or more second-generation stations (R2 STAs); and transmitting the PPDU to the one or more R1 STAs and the one or more R2 STAs, wherein a preamble portion of the PPDU comprises Resource Unit (RU) allocation entries corresponding to the one or more R1 STAs and RU allocation entries corresponding to the one or more R2 STAs.

Abstract: This disclosure describes systems, methods, and devices related to phase shift ToA. A device may determine a first sounding frame received from an responding STA (RSTA), wherein the first sounding frame is received at a first time of arrival (ToA). The device may determine a second sounding frame received from an initiating STA (ISTA), wherein the second sounding frame is received at a second ToA. The device may identify a first reporting frame received from the RSTA. The device may identify a second reporting frame received from the ISTA. The device may extract a first phase shift time estimation from the first reporting frame. The device may extract a second phase shift time estimation from the second reporting frame. The device may determine a ranging location of the device based on the first ToA, the second ToA, the first phase shift time estimation, and the second phase shift time estimation.

Abstract: Methods, systems, articles of manufacture, and apparatus are disclosed to decode zero-value-compression data vectors. An example apparatus includes: a buffer monitor to monitor a buffer for a header including a value indicative of compressed data; a data controller to, when the buffer includes compressed data, determine a first value of a sparse select signal based on (1) a select signal and (2) a first position in a sparsity bitmap, the first value of the sparse select signal corresponding to a processing element that is to process a portion of the compressed data; and a write controller to, when the buffer includes compressed data, determine a second value of a write enable signal based on (1) the select signal and (2) a second position in the sparsity bitmap, the second value of the write enable signal corresponding to the processing element that is to process the portion of the compressed data.

Abstract: This disclosure describes systems, methods, and devices related to an extreme high throughput (EHT) signaling structure. A device may establish a communication channel with one or more station devices (STAs). The device may generate an extreme high throughput signal field (EHT-SIG) of a header, wherein the EHT-SIG field comprises information associated with resource allocations (RUs). The device may generate a frame comprising the header. The device may assign a first RU to a first station device. The device may assign a second RU to the first station device, wherein the first RU or the second RU is an aggregation of a 26-tome RU and a neighboring RU. The device may cause to send the frame to the first station device.

Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.

Abstract: Low latency neural network models are provided that can be used for speech processing. The neural networks allow for real-time inference of CNN models without an increase in computer complexity or memory footprint. Buffers are used for upsampling, and the depth of the convolutions varies by frame number. In some examples, a condition is applied within the convolution block to determine a depth of convolutions based on the frame number. In some examples, the network includes multiple convolution sub-model blocks, each having a different depth, and a table is used to select the convolution sub-model block for each frame based on the frame number. The neural networks can be used for speech enhancement tasks such as dynamic noise suppression (DNS), blind source separation (BSS), and Self-Noise Silencers (SNS).

Abstract: Apparatus and method for performing address pre-translation to enhance direct memory access by hardware subsystems is described herein. An apparatus embodiment includes a processor to execute an enqueue instruction to submit, to a hardware subsystem, a job descriptor describing a job to be performed. The job descriptor includes virtual addresses of memory locations in which data required to perform the job are stored. An input-output memory management unit (IOMMU) is to obtain the address translations for the virtual addresses responsive to a pre-translation request from the processor. The address translations is obtained by the IOMMU prior to receiving a memory access request from the hardware subsystem. The IOMMU is to retrieve the data from the memory location using the address translations and to provide the retrieved data to the hardware subsystem to fulfill the request.

Abstract: In one embodiment, an apparatus comprises a log circuit to: identify an input associated with a logarithm operation, wherein the logarithm operation is to be performed by the log circuit using piecewise linear approximation; identify a first range that the input falls within, wherein the first range is identified from a plurality of ranges associated with a plurality of piecewise linear approximation (PLA) equations for the logarithm operation, and wherein the first range corresponds to a first equation of the plurality of PLA equations; compute a result of the first equation based on a plurality of operands associated with the first equation; and return an output associated with the logarithm operation, wherein the output is generated based at least in part on the result of the first equation.

Abstract: Self-test and repair of memory cells is performed in a memory integrated circuit by two separate processes initiated by a memory controller communicatively coupled to the memory integrated circuit. To ensure that the repair process is completed in the event of an unexpected power failure, a first process is initiated by the memory controller to perform a memory Built-in Self Test (mBIST) in the memory integrated circuit and a second process is initiated by the memory controller after the mBIST has completed to perform repair of faulty memory cells detected during the MBIST process. The memory controller does not initiate the repair process if a power failure has been detected. In addition, a repair time associated with the repair process is selected such that the repair time is sufficient to complete the repair process while power is stable, if a power failure occurs after the repair process has been started.

Abstract: In one embodiment, an AC ionic blower apparatus includes a housing defining a hole through the housing, a first electrode formed around the hole, a second electrode formed around the hole, and a dielectric material between the first electrode and the second electrode. The center of the second electrode is offset from the center of the first electrode.

Abstract: Embodiments described herein are generally directed to decentralized proof of creation. According to one embodiment, a blockchain and smart contracts, including a social decentralized identifier (DID) contract and multiple creator contracts owned and controlled by respective creators, are maintained by a proof of creation facilitator service. A first social DID for a creator of a digital artifact is created on the blockchain via the social DID contract. Based at least in part on the first social DID, decentralized proof of creation (e.g., a non-fungible token (NFT)) for the digital artifact is created on the blockchain via a creator contract of the multiple creator contracts deployed by or on behalf of the creator.

Abstract: A port of a computing device is to communicate with another device over a link, the port including physical layer logic of a first protocol, link layer logic of each of a plurality of different protocols, and protocol negotiation logic to determine which of the plurality of different protocols to apply on the link. The protocol negotiation logic is to send and receive ordered sets in a configuration state of a link training state machine of the first protocol, where the ordered sets include an identifier of a particular one of the plurality of different protocols. The protocol negotiation logic is to determine from the ordered sets that a link layer of the particular protocol is to be applied on the link.

Abstract: Techniques and apparatus to provide for interactions between system components are described. In one embodiment, an apparatus to provide a component interface, the apparatus comprising at least one memory, a first component comprising at least one register, logic, at least a portion of comprised in hardware, the logic to define at least one interface field stored in the at least one register, generate an interface with a second component based on the at least one interface field, and receive interface information from the second component via the interface, the interface information comprising at least one value for the at least one interface field.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a first die comprising a first face and a second face; and a second die, the second die comprising a first face and a second face, wherein the second die further comprises a plurality of first conductive contacts at the first face and a plurality of second conductive contacts at the second face, and the second die is between first-level interconnect contacts of the microelectronic assembly and the first die.

Abstract: Examples relate to a Forward Error Correction (FEC) encoder, an FEC decoder, Passive Optical Network (PON) systems, an Optical Line Terminal (OLT), an Optical Networking Unit (ONU), and to corresponding methods and computer programs. A forward-error-correction (FEC) encoder that is suitable for generating FEC data for use with hard-decision input at a receiver and for use with soft-decision input at the receiver is configured to generate the FEC data based on payload bits using a Low-Density Parity-Check (LDPC) code. The generated FEC data is generated using a single LDPC code that is suitable for use with soft-decision input and hard-decision input at the receiver or using one of two LDPC codes that are suitable for soft-decision input and hard-decision input, respectively.

Abstract: Methods to dynamically configure, monitor and govern PCH Chipsets in platforms as extended IO-expander(s) and associated apparatus. A multi-role PCH is provided that may be dynamically configured as a legacy PCH to facilitate booting for platforms without bootable CPUs and as IO-expanders in single-socket and multi-socket platforms. A control entity is coupled to the PCHs and is used to effect boot, reset, wake, and power management operations by exchanging handshake singles with the PCHs and providing control inputs to CPUs on the platforms. The single-socket platform configurations include a platform with a CPU with bootable logic coupled to an IO-expander and a platform with a legacy CPU coupled to a legacy PCH.

Abstract: An embodiment of a semiconductor package apparatus may include technology to determine version information for a new firmware component, read dependency information corresponding to the firmware component, and determine if dependency is satisfied between the new firmware component and one or more other firmware components based on the version information and the dependency information of the new firmware component. Other embodiments are disclosed and claimed.

Abstract: In some embodiments, a given frame or picture may have different shading rates. In one embodiment in some areas of the frame or picture the shading rate may be less than once per pixel and in other places it may be once per pixel. Examples where the shading rate may be reduced include areas where there is motion and camera defocus, areas of peripheral blur, and in general, any case where the visibility is reduced anyway. The shading rate may be changed in a region, such as a shading quad, by changing the size of the region.

Abstract: Self-aligned gate endcap (SAGE) architectures having gate or contact plugs, and methods of fabricating SAGE architectures having gate or contact plugs, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin. A second gate structure is over a second semiconductor fin. A gate endcap isolation structure is between the first and second semiconductor fins and laterally between and in contact with the first and second gate structures. A gate plug is over the gate endcap isolation structure and laterally between the first gate structure and the second gate structure. A crystalline metal oxide material is laterally between and in contact with the gate plug and the first gate structure, and laterally between and in contact with the gate plug and the second gate structure.

Abstract: Disclosed embodiments are related to beam management in cellular communication networks, and in particular, provide a new transmission (Tx) beamforming indication based on the flexible Tx beam-forming assignment on the corresponding reference signal configured in a transmission configuration indicator (TCI) state for downlink (DL) or spatial relation information in the uplink (UL). The Tx beam-forming on the reference signal of the TCI state configured for the DL physical channel/reference signal can be updated based on reported Tx beam in the UL or using UL measurements from Sounding Reference Signal (SRS) transmission. Similarly, spatial relation information configuration used to indicate Tx beam-forming in the UL, may be also updated based on the reference signal measurements in DL or by suing Downlink Control Information (DCI) based beam indication in a scheduling request indicator (SRI). Other embodiments may be described and/or claimed.

Abstract: An extension device is positioned within a point-to-point link to connect two devices, where the extension device includes error detection circuitry to detect a set of errors at the extension device. The extension device further includes memory to store an event register, where the extension device is to write data to the event register to describe detection of an error by the error detection circuitry. The extension device further includes a transmitter to transmit a notification signal to indicate the detection of the error and presence of data in the evert register associated with the error.