Intel Patents

Intel Corporation designs and manufactures microprocessors and chipsets for computing and communications equipment manufacturers. Its products may be found in desktops, servers, tablets, smartphones and other devices.

Intel Patents by Type
  • Intel Patents Granted: Intel patents that have been granted by the United States Patent and Trademark Office (USPTO).
  • Intel Patent Applications: Intel patent applications that are pending before the United States Patent and Trademark Office (USPTO).
  • Patent number: 7723951
    Abstract: The embodiments of the invention relate to a novel apparatus and method for a battery charging system in a shared environment, as well as for monitoring battery usage and tracking battery location. In one embodiment, the battery charging chute comprises a housing configured to receive a battery via an insertion slot and configured to dispense a battery through a dispensing slot. Within the housing, charging terminals are disposed is a spaced or continuous manner, to come in contact with the charging terminals on batteries inserted into the housing. Optionally, solenoid-controlled gates may be employed at the insertion slot and dispensing slot, to inhibit the removal or insertion of batteries from the incorrect location, to ensure that the battery with the longest residence time in the chute is dispensed to a user. The housing may also include a radio-frequency identification tag reader to permit inventorying and tracking of batteries inserted into the housing.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: May 25, 2010
    Assignee: Intel Corporation
    Inventor: David Poisner
  • Patent number: 7725118
    Abstract: Embodiments of a multi-radio wireless communication device having a Worldwide Interoperability for Microwave Access (WiMax) radio module and a Bluetooth (BT) radio module and methods for communicating are generally described herein. Other embodiments may be described and claimed. In some embodiments, a WiMax active signal is asserted by a coexist controller of the WiMax radio module during receipt of a downlink subframe, and the BT radio module aligns a BT slot boundary of either master-to-slave or slave-to-master slot based on timing information conveyed by the WiMax active signal. The WiMax active signal may be de-asserted by the coexist controller during transmission of an uplink subframe by the WiMax radio module.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: May 25, 2010
    Assignee: Intel Corporation
    Inventors: Xue Yang, Eran Sudak, Xingang Guo, Hsin-Yuo Liu
  • Patent number: 7725085
    Abstract: Apparatus and systems, a well as methods and articles, may operate to determine whether to communicate using a space-time communications technique responsive to an indication derived from processing a short time sequence.
    Type: Grant
    Filed: May 9, 2006
    Date of Patent: May 25, 2010
    Assignee: Intel Corporation
    Inventor: Sondur Lakshmipathi
  • Patent number: 7725511
    Abstract: A biometric keyboard or other input device, such as a keypad or touch screen, may be part of an input mechanism for inputting user information to a computing system. The mechanism may include biometric sensors associated with the buttons or keys of the input device. A mapping scheme may be used such that the input value forwarded to a processing resource when a user activates one or more of the buttons or keys varies depending on which digit (finger, toe, etc.) was used to activate the key(s) or button(s). Other embodiments are also described and claimed.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: May 25, 2010
    Assignee: Intel Corporation
    Inventor: Zafer Kadi
  • Patent number: 7725886
    Abstract: In general, in one aspect, the disclosure describes a method of determining if a first query for data related to a protocol data unit in a first table is a query to a table merged into a combination table formed from multiple tables. If so, the method can generate a second query for the first query for data stored by the combination table.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: May 25, 2010
    Assignee: Intel Corporation
    Inventors: Aaron R. Kunze, Erik J. Johnson, James L. Jason, Harrick M. Vin
  • Patent number: 7725887
    Abstract: In a method for reducing code size, replaceable subsets of instructions at first locations in areas of infrequently executed instructions in a set of instructions and target subsets of instructions at second locations in the set of instructions are identified, wherein each replaceable subset matches at least one target subset. If multiple target subsets of instructions match one replaceable subset of instructions, one of the multiple matching target subsets is chosen as the matching target subset for the one replaceable subset based on whether the multiple target subsets are located in regions of frequently executed code. For each of at least some of the replaceable subsets of instructions, the replaceable subset of instructions is replaced with an instruction to cause the matching target subset of instructions at the second location to be executed.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: May 25, 2010
    Assignee: Intel Corporation
    Inventors: Youfeng Wu, Mauricio Breternitz, Jr.
  • Patent number: 7721060
    Abstract: Some embodiments of the invention implement point-to-point memory channels that virtually eliminate the need for mandatory synchronization cycles for a derived clocking architecture by tracking the number of data transitions on inbound and outbound data lanes to make sure the minimum number of transitions occur. Other embodiments of the invention perform data inversions to increase the likelihood of meeting the minimum data transition density. Still other embodiments are described in the claims.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventor: Robert M. Ellis
  • Patent number: 7719057
    Abstract: Techniques associated with providing multiple gate insulator thickness for a semiconductor device are generally described. In one example, an apparatus includes a semiconductor fin having an impurity introduced to at least a first side of the fin, a first oxide having a first thickness coupled with the first side of the fin, and a second oxide having a second thickness coupled with a second side of the fin, the second thickness being different from the first thickness as a result of the impurity introduced to the first side of the fin.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Martin D Giles, David L Kencke, Stephen M Cea
  • Patent number: 7721148
    Abstract: Disclosed is a communication mechanism among hardware, firmware and system software in order to redirect interrupts or other hardware events to only one thread execution context of an error domain for a multi-threaded processing system. Other embodiments are also described and claimed.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Scott Brenden, Suresh Marisetty, Kushagra Vaid
  • Patent number: 7718528
    Abstract: A semiconductor process technique to help reduce semiconductor process effects, such as undesired line edge roughness, insufficient lithographical resolution, and limited depth of focus problems associated with the removal of a photoresist layer. More particularly, embodiments of the invention use a photoacid generator (PAG) material in conjunction with a sacrificial light absorbing material (SLAM) to help reduce these and other undesired effects associated with the removal of photoresist in a semiconductor manufacturing process. Furthermore, embodiments of the invention allow a PAG to be applied in a semiconductor manufacturing process in an efficient manner, requiring fewer processing operations than typical prior art techniques.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Robert P. Meagley, Heidi B. Cao, Kevin P. O'Brien
  • Patent number: 7720159
    Abstract: In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Jed D. Griffin, Jerry G Jex, Arnaud J. Forestier, Kersi H. Vakil, Abhimanyu Kolla
  • Patent number: 7720036
    Abstract: Communication using a first and a second frequency band in a wireless network is described herein. The first frequency band may be associated with a first beamwidth while the second frequency band may be associated with a second beamwidth, the first beamwidth being wider than the second beamwidth.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Ali S. Sadri, Alexander Maltsev, Roman Maslennikov, Alexey Khoryaev, Vadim Sergeyev
  • Patent number: 7719982
    Abstract: In some embodiments a switching device is disclosed that includes one or more ingress queues to queue data received from external sources while waiting to forward the data to one or more egress queues. The egress queues queue the data while waiting to transmit the data to external sources. The switching device also includes a switch fabric to provide connectivity between the one or more ingress queues and the one or more egress queues. The switching device further includes an ingress flow-control manager to monitor flow-control state of the one or more ingress queues, and to detect and recover from loss of ON flow-control messages. Other embodiments are otherwise disclosed herein.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventor: Anujan Varma
  • Patent number: 7720135
    Abstract: Disclosed are a system, method and device for negotiating a data transmission mode over an attachment unit interface (DDI). A data transceiver circuit may be coupled to one or more data lanes of the DDI. A negotiation section may receive a link pulse signal on at least one data lane in the DDI during a negotiation period and selectively configure the data transceiver to transmit and receive data on one or more data lanes according to a data transmission mode based upon the received link pulse signal.
    Type: Grant
    Filed: March 15, 2004
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Bradley J. Booth, Luke Chang, Ilango S. Ganga
  • Patent number: 7720161
    Abstract: Embodiments of the present invention can be used to generate a family of core training sequences having desired cross-correlation and out-of-phase auto-correlation properties for a communications system. The family can be generated by selecting seed sequences, so that the worst-case cross-correlation of the seed sequences is below a first initial threshold and the worst-case out-of-phase auto-correlation of the seed sequences is below a second initial threshold. Then, sequence families can be generated by inserting additional symbols into a corresponding seed sequence. Then, reduced sequence families can be generated by eliminating those sequences from the sequence families that have a worst-case out-of-phase auto-correlation above a third threshold. A sequence is selected from each reduced sequence family, so that the worst-case cross-correlation of the selected sequences is below a fourth threshold.
    Type: Grant
    Filed: July 9, 2002
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Mithat C. Dogan, Mitchell D. Trott
  • Patent number: 7719084
    Abstract: An embodiment is an inductor that may include a laminated material structure to decrease eddy currents therein that may limit the operation of the inductor at high frequency. An embodiment may employ electroless plating techniques to form a layer or layers of magnetic material within the laminated material structure, and in particular those magnetic layers adjacent to insulator layers.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Patent number: 7719993
    Abstract: A wireless network access point can operate as a closed loop MIMO device when communicating with a station that is operating as an open loop MIMO device. Transmit/receive chains in the access point are calibrated to support aggregate channel reciprocity.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Qinghua Li, Xintian E. Lin
  • Patent number: 7718479
    Abstract: In a metal gate replacement process, a stack of at least two polysilicon layers or other materials may be formed. Sidewall spacers may be formed on the stack. The stack may then be planarized. Next, the upper layer of the stack may be selectively removed. Then, the exposed portions of the sidewall spacers may be selectively removed. Finally, the lower portion of the stack may be removed to form a T-shaped trench which may be filled with the metal replacement.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew V. Metz, Suman Datta, Uday Shah, Robert S. Chau
  • Patent number: 7718904
    Abstract: A shock load applied to a solder ball may be cushioned by providing a viscoelastic material in association with the solder ball. The viscoelastic material dampens shock loads applied to the solder ball and reduces the rate of failure between the solder ball and the rest of the package.
    Type: Grant
    Filed: November 15, 2005
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Rahul N. Manepalli, Sairam Agraharam
  • Patent number: 7721077
    Abstract: A computing system may support an endian toggle register (ETR) and the endianess of the endian toggle register may be designated using a set endian bit (SEB) or a clear endian bit (CEB) instruction. An endian conversion is performed on the data that is moved into and moved out of the ETR. However, if the destination memory is an endian toggle disabled memory, the contents of the ETR may be transferred to the endian toggle disabled memory without performing the endian conversion. A compiler supported on the computing system may comprise an endian storage class to perform endian conversion, transparently, using high-level languages.
    Type: Grant
    Filed: October 16, 2007
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventor: Gurumurthy Rajaram
  • Patent number: 7721150
    Abstract: Provided are techniques for failover when at least one of a first network adapter and a data path through the first network adapter fails, wherein the first network adapter is connected to a filter driver, and wherein the first network adapter is connected to a second network adapter. With the filter driver, a path fail notification is received that at least one of the first network adapter and the data path through the first network adapter has failed. With the filter driver, packets directed to the first network adapter are rerouted to the second network adapter.
    Type: Grant
    Filed: March 19, 2004
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Alexander Belyakov, Mikhail Sennikovsky, Alexey Drozdov
  • Patent number: 7719540
    Abstract: A method and apparatus for rendering three-dimensional graphics using a streaming render-cache with a multi-threading, multi-core graphics processor are disclosed. The graphics processor includes a streaming render-cache and render-cache controller to maintain the order in which threads are dispatched to the graphics engine, and to maintain data coherency between the render-cache and the main memory. The render-cache controller blocks threads from being dispatched to the graphics engine out of order by only allowing one sub-span to be in-flight at any given time.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Thomas A. Piazza, Prasoonkumar Surti
  • Patent number: 7721051
    Abstract: Method and apparatus to improve cache performance using interarrival times between demand requests are described.
    Type: Grant
    Filed: October 25, 2004
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventor: Michael K. Eschmann
  • Patent number: 7718216
    Abstract: A method for low temperature bumping is disclosed. A resin capable of being cross-linked by free-radical or cationic polymerization at low temperature is provided. Electrically conductive particles are then added to the resin to form a mixture. The mixture is then activated by heat or exposure to light to polymerize the mixture. In an alternative embodiment, a vinyl ether resin is used, to which electrically conductive particles are added. The mixture is polymerized by exposure to light.
    Type: Grant
    Filed: March 12, 2007
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Terry Lee Sterrett, Tian-An Chen, Saikumar Jayaraman
  • Patent number: 7720207
    Abstract: An enhanced telephone emulation computer system including a minidialer program for controlling a computer to add telephony functions which can be invoked from whatever active program is currently controlling the computer. The minidialer program controls the computer to alter its processing depending upon the context existing at the time when a mouse click or hot key combination event is detected indicating the user wishes to invoke a telephony function. The minidialer program determines whether the user has highlighted any text or numbers in the active window of the application currently controlling the computer and whether the highlighted material is a name or a phone number, and if a name, whether the name is stored with a phone number in a phone book or file maintained on the computer. Processing and telephony menu options displayed as available also depend upon whether the user is or is not on the phone at the time the mouse click or hot key event occurs.
    Type: Grant
    Filed: January 3, 2005
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Michael D. Stanford, Ronald Scott Langham
  • Patent number: 7719389
    Abstract: Disclosed is a system and method for controlling a resonance frequency of a Film Bulk Acoustic Resonator (FBAR) device. The system includes at least one switching capacitor coupled to the FBAR device and a modulator. The at least one switching capacitor includes at least one capacitor and a switch configuration disposed in series with the FBAR device and the at least one capacitor, which is switch configuration capable of opening and closing connection of the at least one capacitor with the FBAR device. The modulator is coupled to the switch configuration, which generates a switching condition signal based on the manufacturing variation in the FBAR device and the environmental effects on the FBAR device. The switch configuration performs opening and closing of the connection of the at least one capacitor and the FBAR device based on the switching condition signal.
    Type: Grant
    Filed: August 9, 2007
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Hiroyuki Ito, Hasnain Lakdawala, Ashoke Ravi, Krishnamurthy Soumyanath
  • Patent number: 7720490
    Abstract: A method that includes providing, by an active radio of a mobile station that comprises a plurality of radios wherein each radio is associated with a corresponding paging group having its own paging controller, a location update on behalf of an idle radio of the plurality of radios to a paging controller of the active radio's corresponding paging group. The method also includes providing, by the paging controller of the active radio's corresponding paging group, the location update to a paging controller of the idle radio's corresponding paging group. Other embodiments may be described and claimed.
    Type: Grant
    Filed: July 17, 2006
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventor: Muthaiah Venkatachalam
  • Patent number: 7721080
    Abstract: Provided are a method, system, and article of manufacture, wherein instructions stored in an option ROM are copied to the system memory of a computer, wherein the option ROM corresponds to a device that is coupled to the computer. A virtual machine is generated, wherein the virtual machine executes the instructions copied to the system memory to boot the device before any operating system is loaded.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Robert C. Swanson, Vincent J. Zimmer, Larry D. Aaron, Jr., Michael A. Rothman
  • Patent number: 7718025
    Abstract: An embodiment of the present invention includes a plunger, a heating element, and first and second arms. The plunger affixes a first unit to a second unit with adhesive. The first and second units are on a strip of a flexible tape. The strip is on a folding base unit. The folding base unit folds the first unit on top of the second unit. The heating element is attached to the plunger to cure the adhesive. The first and second arms are positioned on first and second sides of the plunger via first and second hinges, respectively, to secure the first and second units underneath the plunger. Another embodiment of the invention includes a first sub-assembly and a second sub-assembly. The first sub-assembly supports a first unit. The first sub-assembly, when activated, folds the first unit on top of a second unit. The first and second units are on a strip of a flexible tape. The second sub-assembly supports the second unit.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Ruel B. Pieda, Alan P. De Ocampo, Rammil Sequido
  • Patent number: 7720440
    Abstract: Embodiments of distributed coordination of a clear channel assessment threshold are presented herein.
    Type: Grant
    Filed: May 18, 2006
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Jing Zhu, Hsin-Yuo Liu
  • Patent number: 7720903
    Abstract: A messaging system may enable a server to assign unique identifiers to a plurality of clients. These identifiers enable a client to determine whether a message is specifically targeted to that client or, as an alternative, whether the client is a member of a group of targeted clients. In one embodiment, each client includes a client identifier that may include code portions that are common to other members of a particular addressable client group. In addition, the client may include agents devoted to particular functions that may be uniquely addressable by the server.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventor: Jeffrey L. Huckins
  • Patent number: 7720930
    Abstract: Systems and methods using network interface card-based (NIC-based) prefetching for host TCP context lookup are disclosed. The process generally includes hashing, by the NIC, a packet received over the network, computing a host hash table cache line in a host memory using the hash value and using a hash table pages table containing host memory physical page addresses of a host hash table, and computing a host context table cache line in a host memory using the hash value and using a context table pages table containing host memory physical page addresses of a host context table. The NIC may be initialized with the hash table pages table and the context table pages table as well as with the a set number of hash node entries in the hash table of the host memory.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventor: David B. Minturn
  • Patent number: 7721076
    Abstract: Method, apparatus and system embodiments provide a register to track the oldest exception event or sticky event in a processor. The processor may be an out-of-order processor. Dispatched instructions (or micro-ops) may be maintained in a queue, such as a reorder buffer (ROB), for in-order retirement. For at least one embodiment, event information is maintained only in the register and is not maintained in a ROB. For at least one other embodiment, event information is maintained in a ROB entry for some events and in the register for others. For such latter embodiment, a retire engine takes the contents of both the ROB entry and the register into account when determining whether to take an exception or otherwise initiate a handling sequence during in-order instruction retirement. Other embodiments are also described and claimed.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Avinash Sodani, Vijaykumar B. Kadgi, Zeev Sperber
  • Patent number: 7721041
    Abstract: Disclosed is a pseudo static random access memory (PSRAM) and a method for operating the same. The PSRAM includes a multi-bit control register and a multiplexer circuit operatively coupled to the multi-bit control register. The multi-bit control register has a first set of bits reserved for a page control mode of the PSRAM and a second set of bits reserved for a bus control mode of the PSRAM. The multiplexer circuit activates one of the page control mode and the bus control mode of the PSRAM based on a logic level of an address bit inputted to the multiplexer circuit.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventor: Reza Jazayeri
  • Patent number: 7720337
    Abstract: In general, in one aspect, a method includes forming conductive layers on a wafer. A through cavity is formed in alignment with the conductive layers. The through cavity is to permit an optical signal from an optical waveguide within an optical connector to pass therethrough. Alignment holes are formed on each side of the through cavity to receive alignment pins. The wafer having the conductive layers, the through cavity in alignment with the conductive layers, and the alignment holes on each side of the through cavity forms an optical-electrical (O/E) interface. An O/E converter is mounted to the metal layers in alignment with the through cavity. The alignment pins and the alignment holes are used to passively align the optical waveguide and the O/E converter.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Daoqiang Lu, Henning Braunisch
  • Patent number: 7720470
    Abstract: Dedicated pilot signals are transmitted from a transmitting device to a receiving device through a multicarrier MIMO channel in addition to data signals and common pilot signals. The dedicated pilot signals may be used by the receiving device to validate whether a predetermined beamforming matrix (i.e., a beamforming matrix identified by the receiving device) was used by the transmitting device to precode the transmitted data. If a different beamforming matrix was used for the preceding, the receiving device may use this matrix to demodulate the received data.
    Type: Grant
    Filed: June 19, 2006
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Jun Shi, Qinghua Li, Hongmei Sun, Minnie Ho
  • Patent number: 7719109
    Abstract: A linear coefficient of thermal expansion (CTE) mismatch between two materials, such as between a microelectronic die and a mounting substrate, may induce stress at the interface of the materials. The temperature changes present during the process of attaching a die to a mounting substrate can cause cracking and failure in the electrical connections used to connect the die and mounting substrate. A material with a CTE approximately matching the die CTE is introduced in the mounting substrate to reduce the stress and cracking at the electrical connections between the die and mounting substrate. Additionally, this material may comprise thin film capacitors useful for decoupling power supplies.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Mitul Modi, Sudarshan V. Rangaraj, Shankar Ganapathysubramanian, Richard J. Harries, Sankara J. Subramanian
  • Patent number: 7716997
    Abstract: A sensing device is used to consolidate and time-synchronize Intensive Care Unit (ICU) or other clinical data from patient monitoring devices provided by a plurality of different vendors having proprietary event data formats. The automation of logging of events due to external forces applied to patient monitoring devices detected by the sensing device improves the timing in and completeness of nurses' notes. Furthermore, the sensing device provides an easy way to synchronize or consolidate data from multiple vendors' patient monitoring devices.
    Type: Grant
    Filed: September 12, 2007
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventor: Jennifer Healey
  • Patent number: 7721050
    Abstract: In a cache coherency protocol a re-snoop may be utilized to resolve a data request conflict condition. The re-snoop may avoid a conflict resolution phase, which may reduce system inefficiencies.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Herbert H. Hum, Robert Beers
  • Patent number: 7719062
    Abstract: A method for forming a slot contact structure for n-type transistor performance enhancement. A slot contact opening is formed to expose a contact region, and a barrier plug is disposed within a portion of the slot contact opening in order to induce a tensile stress on an adjacent channel region. The remainder of the slot contact opening is filled with a lower resistivity contact metal. Barrier plug deposition temperature can be varied in order to tune the tensile stress on the adjacent channel region.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Kevin J. Fischer, Vinay B. Chikarmane, Brennan L. Peterson
  • Patent number: 7720030
    Abstract: Techniques for explicit feedback delay measurement are described. An apparatus may comprise a processor to generate a steering matrix for transmit spatial processing over a channel, determine a delay time associated with explicit feedback information for the channel, and determine whether to modify the steering matrix with the explicit feedback information based on the delay time. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Trainin B. Solomon, Kasher Assaf, Kaidar Oren, Myszne Jorge, Basson Gal
  • Patent number: 7719251
    Abstract: A switching mode power converter may include a modulation circuit to dynamically control a variable switching frequency of the power converter based on an error voltage of the power converter. The power converter may also include a control circuit connected to the modulation circuit and arranged to dynamically limit an inductor current in the power converter while the switching frequency of the power converter changes. A variable limit on the inductor current may be based on the error voltage of the power converter, a load current of the power converter, or information from a power manager of a system in which the power converter resides. In some implementations, the power converter may also include a disabling circuit to control the modulation circuit to disable the variable switching frequency when a sufficiently large load transient is detected.
    Type: Grant
    Filed: August 6, 2007
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Jaber Abu Qahouq, Lilly Huang
  • Patent number: 7721129
    Abstract: A clock frequency control unit for an integrated circuit (IC) includes a clock generator, a finite state machine (FSM), and a gating circuit (GC). The FSM has at least first and second states corresponding to non-low workload low workload states, respectively. In the first state, the GC provides a clock signal to functional units of the IC with the same frequency as the clock generator output. In the second state, the GC reduces the frequency of the clock signal. In one embodiment, the GC masks out selected cycles of the clock generator output to reduce the clock signal frequency. The FSM monitors the operation of the IC to transition from the first state to the second state when selected “low workload” conditions are detected (e.g., long latency cache miss). Similarly, the FSM transitions from the second state to the first state when selected “non-low workload” conditions are detected.
    Type: Grant
    Filed: January 12, 2006
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Itamar S. Kazachinsky, Doron Orenstein
  • Patent number: 7720854
    Abstract: Techniques are described herein that can be used to access entries in a packed table. An unpacked table includes empty and filled elements. Filled elements can be accumulated and included in a packed table. An element in the packed table can be accessed by considering the location the element would have been located in the unpacked table. The location can be used to determine the location of the element in the packed table.
    Type: Grant
    Filed: August 25, 2006
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventor: Makaram Raghunandan
  • Patent number: 7721013
    Abstract: In one embodiment, the present invention includes a method for providing a command from a keyboard, video and mouse (KVM) system of a first system to a graphics card of the first system via an existing system interface, sampling data from a frame buffer of the graphics card and providing the sampled data to a sample buffer of the KVM system, and processing the sampled data in the KVM system. Also, data to be displayed at a graphics card may be sent as out-of-band (OOB) data from the KVM system. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 21, 2007
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventor: Nimrod Diamant
  • Patent number: 7720075
    Abstract: According to some embodiments, a Gigabit Ethernet link is maintained with a link partner using less than four channels. Embodiments may also establish the Gigabit Ethernet link using four channels, determine that the link is idle, and terminate communication with the link partner over at least one of the four channels.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventor: Avi Costo
  • Patent number: 7719972
    Abstract: Embodiments of methods and apparatus for providing an admission control system in a wireless mesh network are generally described herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Yuan Yuan, Liuyang L. Yang
  • Patent number: 7719878
    Abstract: The write disturb that occurs in polymer memories may be reduced by writing back data after a read in a fashion which offsets any effect on the polarity of bits in bit lines associated with the addressed bit. For example, each time the data is written back, its polarity may be alternately changed. In another embodiment, the polarity may be randomly changed.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Richard L. Coulson, Jonathan C. Lueker, Robert W. Faber
  • Patent number: 7720166
    Abstract: Embodiments of the present invention provide a method, apparatus and system of decoding spatially multiplexed signals. In some demonstrative embodiments the method may include, for example, determining one or more hypothetical values of a transmitted signal of a set of transmitted signals based on one or more respective sets of hypothetical values assigned to a subset of the set of transmitted signals. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Yuval Lomnitz, Yang-Seok Choi
  • Publication number: 20100118028
    Abstract: A system, method and apparatus to provide flexible texture filtering. A programmable texture filtering module is introduced into the graphics processing pipeline of a graphic coprocessor and graphic processor integrated with the host. A program from a defined instruction set may then be loaded into texture processing cores to process texture data consistent with the program.
    Type: Application
    Filed: January 15, 2010
    Publication date: May 13, 2010
    Applicant: Intel Corporation
    Inventor: Kim Pallister