Intel Patents

Intel Corporation designs and manufactures microprocessors and chipsets for computing and communications equipment manufacturers. Its products may be found in desktops, servers, tablets, smartphones and other devices.

Intel Patents by Type
  • Intel Patents Granted: Intel patents that have been granted by the United States Patent and Trademark Office (USPTO).
  • Intel Patent Applications: Intel patent applications that are pending before the United States Patent and Trademark Office (USPTO).
  • Publication number: 20100120132
    Abstract: Embodiments of the invention relate to detecting biological molecules with ultra-sensitivity and convenience. The embodiments are especially directed to utilizing nanoparticles as tags and identifying the tags using dark-field microscopy. The probes containing the nanoparticles can be used in solution or attached to a substrate.
    Type: Application
    Filed: March 31, 2006
    Publication date: May 13, 2010
    Applicant: Intel Corporation
    Inventor: Tae-Woong Koo
  • Publication number: 20100118875
    Abstract: A method and apparatus to perform protocol translation for a modular system may be described.
    Type: Application
    Filed: July 8, 2009
    Publication date: May 13, 2010
    Applicant: INTEL CORPORATION
    Inventors: Gerald Lebizay, David W Gish, Neal C Oliver
  • Patent number: 7715960
    Abstract: A computer built into an automobile displays the owner's manual for the car. The user requests more information about the automobile through the computer, and the additional information is displayed to the user. Information may include a description of a specific function or device of the car, service history, and/or real time status of a component of the car.
    Type: Grant
    Filed: October 8, 2007
    Date of Patent: May 11, 2010
    Assignee: Intel Corporation
    Inventor: Kelan C. Silvester
  • Patent number: 7713858
    Abstract: A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die, an interposer-type structure for a flip-chip, a mounting substrate, or a board. The CNT array is patterned by using a patterned metallic seed layer on the substrate to form the CNT array by chemical vapor deposition. The patterned CNT array can also be patterned by using a patterned mask on the substrate to form the CNT array by growing. A computing system that uses the CNT array for heat transfer from the die is also used.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: May 11, 2010
    Assignee: Intel Corporation
    Inventors: Nachiket Raravikar, Daewoong Suh
  • Patent number: 7714427
    Abstract: Integrate circuit die terminal arrangements and configurations for mounting an integrate circuit die on a package substrate to reduce package transmission paths. In one embodiment, terminals for signals sensitive to trace length outside a die are arranged at the corners of the die. The die is mounted on a package substrate in an angle with respect to a package substrate to point the corners of the die at the edges of the package substrate to reduce trace length outside the die. The center of the die may or may not coincide with the center of the substrate. In one embodiment, when compare to a centered, non-rotated die mounting position, mounting a die with corners pointing at the edges of the package substrate does not cause significant differences in substrate warpage.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: May 11, 2010
    Assignee: Intel Corporation
    Inventors: Chee Wai Wong, Chee Hoo Lee
  • Patent number: 7716409
    Abstract: In one embodiment of the present invention, a method includes identifying a transaction from a first processor to a second processor of a system with a transaction identifier. The transaction identifier may have a value that is less than or equal to a maximum number of outstanding transactions between the two processors. In such manner, a transaction field for the transaction identifier may be limited to n bits, where the maximum number of outstanding transactions is less than or equal to 2n. In various embodiments, such a transaction identifier combined with a source identifier and a home node identifier may form a globally unique transaction identifier.
    Type: Grant
    Filed: April 27, 2004
    Date of Patent: May 11, 2010
    Assignee: Intel Corporation
    Inventors: Herbert H. J. Hum, Aaron T. Spink, Robert G. Blankenship
  • Patent number: 7714432
    Abstract: A semiconductor device is provided that includes one or more ceramic material layers and one or more low dielectric constant (low-K) epoxy layers on top to be electrically coupled to an integrated circuit device, such as a chip die. The resulting ceramic/organic hybrid substrate takes advantage of the thin low-cost, low-K epoxy layer, by routing the dense circuitry from the chip die to the ceramic material layer. In addition, the use of low-K epoxy layer may reduce the number of ceramic material layers required to about three layers, thus significantly reducing the cost of the substrate. Low-K epoxy material layer may be laminated onto the ceramic material layer to reduce throughput time and cost. The ceramic/organic hybrid substrate may also take advantage of the properties of ceramic materials, which have a much more rigid structure than organic materials and a low CTE (coefficient of thermal expansion) that works well with ultra low-K chip dies.
    Type: Grant
    Filed: July 26, 2002
    Date of Patent: May 11, 2010
    Assignee: Intel Corporation
    Inventor: John Tang
  • Patent number: 7715493
    Abstract: Embodiments of a multicarrier transmitter and method of generating an RF signal for transmission are generally described herein. Other embodiments may be described and claimed. In some embodiments, a multicarrier transmitter generates RF signals for transmission using non-linear switching power amplifiers to amplify outphased switching waveforms allowing the multicarrier transmitter to operate more efficiently than some conventional multicarrier transmitters.
    Type: Grant
    Filed: August 14, 2006
    Date of Patent: May 11, 2010
    Assignee: Intel Corporation
    Inventors: Ashoke Ravi, Ravi Naiknaware, Krishnamurthy Soumyanath
  • Patent number: 7714433
    Abstract: In one embodiment, the present invention includes a semiconductor package having a plurality of fan blades embedded within a first surface of the package, where a first group of the fan blades extend from a first side of the package and a second group of the fan blades extend from a second side of semiconductor package. The fan blades may be powered by piezoelectric devices to cause motion of the fan blades. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: May 11, 2010
    Assignee: Intel Corporation
    Inventors: Edoardo Campini, Javier Leija, William Handley
  • Patent number: 7715447
    Abstract: Tone detection includes receiving a series of frames having a signal containing a tone and locating a first frame in the series of frames in which there is at least a partial, tone. The signal energy of the first frame may then be compared to the signal energy of a full tone frame or compared to the signal energy of a frame. A start time of the tone in the signal may then be determined. An end time of the tone in the signal may be determined by locating a last frame in the series of frames. The duration of the tone signal may be determined based on the determined start time and end time of the tone in the signal.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: May 11, 2010
    Assignee: Intel Corporation
    Inventors: Sui Lam, Kai Miao, Amin Rhemtulla
  • Patent number: 7716465
    Abstract: In a processing system with a main partition and a sequestered partition, the main partition sends an interrupt to the sequestered partition before calling an operating system (OS) boot loader for the main partition. The sequestered partition may then enter an interrupt handler. After the sequestered partition enters the interrupt handler, an address line of the processing system may be disabled, and the OS boot loader for the non-sequestered partition may be called. The sequestered partition may then determine whether the address line has been re-enabled. The sequestered partition may remain in the interrupt handler until after the address line has been re-enabled. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: May 11, 2010
    Assignee: Intel Corporation
    Inventor: Saul Lewites
  • Patent number: 7715959
    Abstract: A computer built into an automobile displays the owner's manual for the car. The user requests more information about the automobile through the computer, and the additional information is displayed to the user. Information may include a description of a specific function or device of the car, service history, and/or real time status of a component of the car.
    Type: Grant
    Filed: October 8, 2007
    Date of Patent: May 11, 2010
    Assignee: Intel Corporation
    Inventor: Kelan C. Silvester
  • Patent number: 7716385
    Abstract: A method and architecture for enabling interaction between a remote device and a host computer. A service provided by the remote device is discovered, and a description pertaining to the service is retrieved by the host computer. A network communication link is the established between the remote device and the host computer based on connection information provided by the description. Host-side and client-side software service modules are run on the host and remote devices to enable interaction between the devices using a service protocol that is specific to the service. Various service protocols are provided, including a display service protocol and an input service protocol. Using commands provided by each protocol, the host computer is enabled to control the service remotely by pushing data and appropriate commands to the remote device, whereupon these commands are processed by the client-side service module to perform service operations that employ the sent data.
    Type: Grant
    Filed: August 17, 2006
    Date of Patent: May 11, 2010
    Assignee: Intel Corporation
    Inventors: Ylian Saint-Hilaire, Jim W. Edwards
  • Patent number: 7715931
    Abstract: An alignment mechanism to align a microelectronic device to a socket, the device including an array of contact pads thereon. The mechanism includes a socket system having a socket and a device positioning mechanism disposed adjacent the socket and adapted to position the device in the socket. The mechanism also includes a control system adapted to receive alignment data on a position of the array of contact pads relative to two reference sides of the device, the control system further being adapted to control the device positioning mechanism as a function of alignment data to align the device in the socket.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: May 11, 2010
    Assignee: Intel Corporation
    Inventors: John C. Johnson, Wei-ming Chi
  • Patent number: 7716561
    Abstract: A method and apparatus are provided for error correction of a communication signal. A multiple threshold scheme for iteratively decoding a received codeword includes using a comparison of an updated bit reliability with a threshold to generate a reconstructed version of the received codeword. At each iteration the bit reliability and the reconstructed codeword are updated based on a comparison using a threshold that has been updated for the given iteration. Embodiments include decoding and/or associated encoding methods and apparatus using a threshold having two of more values during the iterative decoding.
    Type: Grant
    Filed: August 22, 2006
    Date of Patent: May 11, 2010
    Assignee: Intel Corporation
    Inventors: Andrey Vladimirovich Belogolovyi, Evguenii A. Kruk, Peter Vladimirovich Trifonov
  • Patent number: 7714909
    Abstract: A method and apparatus are provided for annotating video and audio media with supplementary content for post video processing. In one embodiment, the invention may include maintaining a current state of auxiliary information regarding a sequence of video frames, the sequence of video frames being encoded as a video bit stream having video frame data for each respective video frame of the sequence of video frames. It may further include comparing the current state of auxiliary information with auxiliary information regarding a current video frame of the sequence of video frames to determine differential information, and annotating the differential information to the video bit stream as an annotation to the video frame data for the current video frame.
    Type: Grant
    Filed: January 14, 2004
    Date of Patent: May 11, 2010
    Assignee: Intel Corporation
    Inventors: Christopher J. Lord, Fernando C. M. Martins, Brian R. Nickerson
  • Patent number: 7716536
    Abstract: Techniques to cause a point-to-point link between system components to engage in a negotiation process that may lead to the link transitioning from an active state in which data may be transmitted between system components to a low power state where data may not be transmitted. The negotiation process may occur between each pair of nodes within an electronic system that are interconnected via point-to-point link. The negotiation may ensure that there are no pending transactions or transactions that may occur within an upcoming period of time. Through this negotiation each component acknowledges and agrees to transition the link to the low power state.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: May 11, 2010
    Assignee: Intel Corporation
    Inventors: Shaun M. Conrad, Robert J. Safranek, Selim Bilgin
  • Patent number: 7713803
    Abstract: A method of fabricating a quantum well device includes forming a diffusion barrier on sides of a delta layer of a quantum well to confine dopants to the quantum well.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: May 11, 2010
    Assignee: Intel Corporation
    Inventors: Been-Yih Jin, Jack T. Kavalieros, Suman Datta, Amlan Majumdar, Robert S. Chau
  • Patent number: 7714397
    Abstract: A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.
    Type: Grant
    Filed: July 25, 2006
    Date of Patent: May 11, 2010
    Assignee: Intel Corporation
    Inventors: Scott A. Hareland, Robert S. Chau, Brian S. Doyle, Suman Datta, Been-Yih Jin
  • Patent number: 7714430
    Abstract: In one embodiment, the present invention includes a semiconductor package with lossy material inserts. The lossy material inserts may reduce electronic noise such as package resonance. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: May 11, 2010
    Assignee: Intel Corporation
    Inventors: Xiang Yin Zeng, Daoqiang (Daniel) Lu, Jiangqi He, Jiamiao(John) Tang
  • Patent number: 7716421
    Abstract: A method according to one embodiment may include partitioning a plurality of core processors into a main partition comprising at least one processor core capable of executing an operating system and an embedded partition comprising at least one different processor core. The main partition and embedded partition may communicate with each other through a bridge. The embedded partition of this embodiment may be capable of: mapping two or more mass storage systems, coupled to the embedded partition, into a single logical device; presenting the logical device to the bridge; and receiving at least one I/O request, generated by the main partition and directed to the logical device, and in response to the I/O request, the embedded partition may be further capable of communicating with at least one of the two or more mass storage systems using at least one communication protocol to process said I/O request; and reporting the status of the I/O request to the main partition, via the bridge.
    Type: Grant
    Filed: May 6, 2008
    Date of Patent: May 11, 2010
    Assignee: Intel Corporation
    Inventors: Vincent J. Zimmer, Michael A. Rothman
  • Patent number: 7713839
    Abstract: Electronic assemblies and methods for forming assemblies including a diamond substrate are described. One embodiment includes providing a diamond support and forming a porous layer of SiO2 on the diamond support. A diamond layer is formed by chemical vapor deposition on the porous layer so that the porous layer is between the diamond support and the diamond layer. A polycrystalline silicon layer is formed on the diamond layer. The polycrystalline silicon layer is polished to form a planarized surface. A semiconductor layer is coupled to the polysilicon layer. After coupling the semiconductor layer to the polysilicon layer, the diamond support is detached from the diamond layer by breaking the porous layer. The semiconductor layer on the diamond layer substrate is then further processed to form a semiconductor device.
    Type: Grant
    Filed: October 6, 2004
    Date of Patent: May 11, 2010
    Assignee: Intel Corporation
    Inventors: Chuan Hu, Gregory M. Chrysler, Daoqiang Lu
  • Patent number: 7715442
    Abstract: Embodiments of the present invention provide a method, apparatus, and system of wireless transmission with frame alignment. For example, a method in accordance with demonstrative embodiments of the invention may include synchronizing between a transmitter using a first modulation scheme, which may have multiple frame formats, and a receiver using a second modulation scheme, by calculating a transmission time that aligns an inter frame space start time of the first and second modulation schemes. Other features are described and claimed.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: May 11, 2010
    Assignee: Intel Corporation
    Inventors: Solomon B. Trainin, Assaf Kasher
  • Patent number: 7715676
    Abstract: An optical grating is disposed on a waveguide to redirect light from the interior of the waveguide through the opposite side of the waveguide from the grating. In one embodiment the waveguide, the grating, and an optical sensor are combined in a single monolithic structure. In another embodiment, an absorbing layer is directly connected to the waveguide in the region of the grating. In still another embodiment, efficiency of the grating is improved by having a high index contrast between the refractive index of the grating and the refractive index of the cladding disposed over the grating, and by having an appropriately sized discontinuity in the grating.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: May 11, 2010
    Assignees: Intel Corporation, Massachusetts Institute of Technology
    Inventors: Jun-Fei Zheng, Kazumi Wada, Jurgen Michel, Donghwan Ahn, Lionel C. Kimerling
  • Patent number: 7714753
    Abstract: One embodiment of the invention concerns performing renormalization in content adaptive binary arithmetic coding (CABAC) only after multiple bins are processed.
    Type: Grant
    Filed: December 11, 2007
    Date of Patent: May 11, 2010
    Assignee: Intel Corporation
    Inventor: Ning Lu
  • Patent number: 7716464
    Abstract: A method and apparatus is described herein for fault resilient booting of a platform. Upon booting the platform, any boot routines marked are skipped. A current boot routine to be executed in a boot sequence is registered in nonvolatile memory. An attempt to execute the current boot routine is made. If the attempt is successful, the next boot entry is determined and skipped or executed, based on whether it is marked. However, if the execution fails the current boot routine is marked and, upon subsequent execution of the boot sequence, skipped.
    Type: Grant
    Filed: June 23, 2005
    Date of Patent: May 11, 2010
    Assignee: Intel Corporation
    Inventors: Michael A. Rothman, Robert C. Swanson, Vincent J. Zimmer
  • Patent number: 7715208
    Abstract: A configurable multi-faceted input/output (I/O) panel may be used in a computer or electronic device to present multiple I/O interfaces to a user. The configurable multi-faceted I/O panels may be configured by a user such that one of a plurality of different I/O faces is accessible to the user. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: May 11, 2010
    Assignee: Intel Corporation
    Inventors: Edoardo Campini, Javier Leija, William Handley
  • Patent number: 7716395
    Abstract: A mechanism and technique to transfer data between a communication device and media hardware in a computing device. More particularly, an embodiment of the invention uses a quality of service to assure deterministic latencies in direct data transfers between a memory buffer and each of a communication device and an audio hardware controller.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: May 11, 2010
    Assignee: Intel Corporation
    Inventor: Prashant Sethi
  • Patent number: 7714870
    Abstract: A method and apparatus employing selectable hardware accelerators in a data driven architecture are described. In one embodiment, the apparatus includes a plurality of processing elements (PEs). A plurality of hardware accelerators are coupled to a selection unit. A register is coupled to the selection unit and the plurality of processing elements. In one embodiment, the register includes a plurality of general purpose registers (GPR), which are accessible by the plurality of processing elements, as well as the plurality of hardware accelerators. In one embodiment, at least one of the GPRs includes a bit to enable a processing element to enable access a selected hardware accelerator via the selection unit.
    Type: Grant
    Filed: June 23, 2003
    Date of Patent: May 11, 2010
    Assignee: Intel Corporation
    Inventors: Louis A. Lippincott, Patrick F. Johnson
  • Publication number: 20100111013
    Abstract: Briefly, in accordance with one or more embodiments, a femto access point scans an area of a network to find a serving base station in the area, requests one or more physical link profiles from a network server on the network, receives one or more physical link profiles from the network server in response to the requesting, determines which one of the physical link profiles exhibit a lower amount of interference with the serving base station, and then operates with the physical link profile determined to exhibit a lower amount of interference with the serving base station.
    Type: Application
    Filed: October 19, 2009
    Publication date: May 6, 2010
    Applicant: INTEL CORPORATION
    Inventor: Joey Chou
  • Patent number: 7712091
    Abstract: A method and system for optimizing the execution of a software loop is provided. The method involves the determination of an edge in a critical recurrence cycle in the software loop. The edge is a dependency link between two instructions and contains a dependee and a dependent. The dependee is an instruction that produces a result, and the dependent is an instruction that uses the result. The method further involves performing predicate promotion of at least one of the dependee and the dependent if one or more pre-determined conditions are met.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: May 4, 2010
    Assignee: Intel Corporation
    Inventors: Kalyan Muthukumar, Robyn A. Sampson, Daniel Lavery
  • Patent number: 7709744
    Abstract: Venting for component mounting pads of surface mount circuit boards allows the escape of gases from the junction between an electrical component and its associated mounting pad during soldering and facilitates a more complete and effective solder joint between the component base and pad. The venting may be accomplished by either one or more through holes in the board through the pads to allow undesirable gases to escape to the underside of the board, or by one or more solder free channels formed in the pad to allow the gases to escape through the periphery of the pad.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: May 4, 2010
    Assignee: Intel Corporation
    Inventors: Richard C. Schaefer, Steven Pollock, Charles M. Bailley, Mike Lowe, Andrew J. Balk, John G. Oldendorf
  • Patent number: 7710781
    Abstract: A wireless device that includes a memory device having an engine to execute a voting algorithm to average a memory cell data sensing result over time to provide a charge placement in the memory cell.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: May 4, 2010
    Assignee: Intel Corporation
    Inventors: Rezaul Haque, Darshak A. Udeshi, Karthi Ramamurthi, Nathan C. Chrisman, Aliasgar S. Madraswala, Kevin P. Flanagan
  • Patent number: 7712013
    Abstract: In an embodiment, a method includes performing a redundancy check to determine if a baseline bit sequence is compliant. When the baseline bit sequence is not compliant, the method additionally includes performing an iterative process until a compliant, candidate bit sequence is identified. The iterative process includes identifying one or more existing branches within a conceptual tree diagram, calculating scores for potential paths branching from the one or more existing branches, and performing a subsequent redundancy check on a next candidate bit sequence, which corresponds to a potential path that has a next lowest score, to determine if the next candidate bit sequence is compliant.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: May 4, 2010
    Assignee: Intel Corporation
    Inventors: Meir Griniasty, Moti Altahan
  • Patent number: 7710234
    Abstract: An embodiment is a magnetic via. More specifically, an embodiment is a magnetic via that increases the inductance of, for example, an integrated inductor or transformer while mitigating eddy currents therein that may limit the operation of the inductor or transformer at high frequency.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: May 4, 2010
    Assignee: Intel Corporation
    Inventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Kamik
  • Patent number: 7710210
    Abstract: An apparatus is provided that includes an injection locked oscillator and a transmitting device. The injection locked oscillator to receive a first clock signal and to provide a second clock signal by skewing the first clock signal. The transmitting device to receive an input signal and to receive the second clock signal as a clocking signal, the transmitting device to transmit an output signal based on the received clocking signal.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: May 4, 2010
    Assignee: Intel Corporation
    Inventors: Bryan K. Casper, Mozhgan Mansuri, Frank O'Mahony, James E. Jaussi
  • Patent number: 7711960
    Abstract: Methods and arrangements to control access to cryptographic keys and to attest to the approved configurations of computer platforms able to access these keys, which include trusted platform modules (TPMs) are contemplated. Embodiments include transformations, code, state machines or other logic to control access to a cryptographic key by creating an authorization blob locking authorization data to access the cryptographic key to platform configuration register (PCR) values of a TPM, the PCR values representing a configuration of a computing platform. Embodiments may also involve generating a first TPM cryptographic key bound to PCR values, receiving a second TPM cryptographic key owned by software, and receiving evidence of the identity of an upgrade service controlling the upgrading of the software.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: May 4, 2010
    Assignee: Intel Corporation
    Inventor: Vincent Scarlata
  • Patent number: 7711975
    Abstract: In some embodiments it is determined if a speed of a Universal Serial Bus cable of greater than 480 Mb per second is supported at each end of the Universal Serial Bus cable, the length of the Universal Serial Bus cable is calculated, and the speed of the Universal Serial Bus cable is increased beyond 480 Mb per second in response to the determining and the calculating. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: May 4, 2010
    Assignee: Intel Corporation
    Inventor: James J. Choate
  • Patent number: 7709909
    Abstract: A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: May 4, 2010
    Assignee: Intel Corporation
    Inventors: Mark L. Doczy, Gilbert Dewey, Suman Datta, Sangwoo Pae, Justin K. Brask, Jack Kavalieros, Matthew V. Metz, Adrian B. Sherrill, Markus Kuhn, Robert S. Chau
  • Patent number: 7711939
    Abstract: A source terminated serial link can recover from a low power mode by turning on multiple current-mode drivers in a phased sequence where the phased sequence is related to a resonant characteristic of a power supply net.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: May 4, 2010
    Assignee: Intel Corporation
    Inventors: Karthisha S. Canagasaby, Ken Drottar, David S. Dunning, Sanjay Dabral
  • Patent number: 7711062
    Abstract: Methods and apparatus are described herein to provide for the decoding of signals in a MIMO communications system. Other embodiments may include a method of deriving a list of possible data vectors and corresponding metrics given a received signal vector and provide the list to a soft bits calculator. Further embodiments include a decoding apparatus that includes a shift and scale module, a linear receiver module, a list generator module and a lattice reduction module. The decoding apparatus may additionally include a soft bits calculator, in further embodiments.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: May 4, 2010
    Assignee: Intel Corporation
    Inventor: Ilan Hen
  • Patent number: 7711898
    Abstract: Embodiments of the present invention relate to a system and method for implementing functions of a register translation table of a computer processor, with reduced area requirements as compared to known arrangements. In one embodiment, an apparatus may comprise a register alias table cache to map a logical register to a physical register. The register alias table cache may have a capacity corresponding to a subset of architectural logical registers. The apparatus may further comprise store logic coupled to the cache to perform operations to save an existing content of the physical register if a cache entry corresponding to the logical register is evicted from the cache. The apparatus may also comprise load logic coupled to the cache to perform operations to load a content to the physical register and to form a new entry in the cache if a needed mapping is not present in the cache.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: May 4, 2010
    Assignee: Intel Corporation
    Inventors: Avinash Sodani, Stephan J. Jourdan, Samie B. Samaan
  • Patent number: 7711659
    Abstract: A system may include construction of observation vectors based on a plurality of power samples indicating past power consumption of a device and a plurality of temperature samples indicating past temperatures of the device, determination of an estimated temperature of the device based on fuzzy reasoning models comprising the observation vectors and a fan control parameter vector; measurement of a temperature of the device, determination of an error based on the estimated temperature and the measured temperature, and adaptation of the fan control parameter vector using a recursive least squares algorithm based on the error. The fans may be controlled based on the fan control parameter vector.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: May 4, 2010
    Assignee: Intel Corporation
    Inventors: Rafael de la Guardia, Willem M. Beltman
  • Patent number: 7710430
    Abstract: Methods, systems and data structures produce a rasterizer. A graphical state is detected on a machine architecture. The graphical state is used for assembling a shell rasterizer. The machine architecture is used for selecting replacement logic that replaces portions of shell logic in the shell rasterizer. The machine architecture is used for selectively inserting memory management logic into portions of the shell logic to produce.
    Type: Grant
    Filed: October 21, 2008
    Date of Patent: May 4, 2010
    Assignee: Intel Corporation
    Inventors: William A. Hux, Stephen Junkins
  • Patent number: 7709866
    Abstract: In one embodiment of the invention, contact patterning may be divided into two or more passes which may allow designers to control the gate height critical dimension relatively independent from the contact top critical dimension.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: May 4, 2010
    Assignee: Intel Corporation
    Inventors: Nadia Rahhal-Orabi, Charles H. Wallace, Alison Davis, Swaminathan Sivakumar
  • Patent number: 7710972
    Abstract: A table descriptor is associated with a table and referenced to provide access to the table. The table descriptor includes a first portion identifying information about the table and a second portion identifying one or more locations of the table in memory.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: May 4, 2010
    Assignee: Intel Corporation
    Inventor: Rajaram Gurumurthy
  • Patent number: 7710968
    Abstract: A first logic offloads some network protocol unit formation tasks to a second logic. The first logic may request that data be transmitted using a Direct Data Placement (DDP) compatible network protocol unit. The first logic may provide the data as well as other information relevant to forming the DDP compatible network protocol unit. The second logic may form portions of the DDP compatible network protocol unit using the data and the provided information.
    Type: Grant
    Filed: May 11, 2006
    Date of Patent: May 4, 2010
    Assignee: Intel Corporation
    Inventors: Linden Cornett, Steven King, Sujoy Sen, Parthasarathy Sarangam, Frank Berry
  • Patent number: 7710325
    Abstract: Provided is an antenna comprising a first dielectric resonator antenna operative within a first frequency band, a second dielectric resonator antenna operative within a second frequency band, and a feeding structure electrically coupled to the first and second dielectric resonator antennas to receive and transmit signals at the first and second frequency bands through the first and second dielectric resonator antennas.
    Type: Grant
    Filed: August 15, 2006
    Date of Patent: May 4, 2010
    Assignee: Intel Corporation
    Inventor: Dajun Cheng
  • Patent number: 7710904
    Abstract: An apparatus including a ring network, a plurality of nodes on the ring network to act as senders, a node on the ring network to act as a receiver, the receiver having receiver logic to place a token on the ring, the token further having an indication of an activation status, and network logic to pass the token along the ring network from each node to the next after the token is placed on the ring network and to activate the token by setting the indication of the activation status to a value indicating that the token is active at a location on the ring determined so that over a defined period of time, the token is activated in proximity to each sender at approximately the same frequency.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: May 4, 2010
    Assignee: Intel Corporation
    Inventor: George Chrysos
  • Patent number: 7709247
    Abstract: Provided herein are methods and systems for detecting biomolecular binding events using gigahertz or terahertz radiation. The methods and systems use low-energy spectroscopy to detect biomolecular binding events between molecules in an aqueous solution. The detected biomolecular binding events include, for example, nucleic acid hybridizations, antibody/antigen binding, and receptor/ligand binding.
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: May 4, 2010
    Assignee: Intel Corporation
    Inventors: Tae-Woong Koo, Andrew Berlin, Ken Salsman, Brian Ostrovsky