Intel Patents

Intel Corporation designs and manufactures microprocessors and chipsets for computing and communications equipment manufacturers. Its products may be found in desktops, servers, tablets, smartphones and other devices.

Intel Patents by Type
  • Intel Patents Granted: Intel patents that have been granted by the United States Patent and Trademark Office (USPTO).
  • Intel Patent Applications: Intel patent applications that are pending before the United States Patent and Trademark Office (USPTO).
  • Patent number: 7707399
    Abstract: Embodiments of the present invention provide adjustments of the depiction of a user interface upon a computing environment's change in state.
    Type: Grant
    Filed: April 23, 2004
    Date of Patent: April 27, 2010
    Assignee: Intel Corporation
    Inventor: Geoffrey W. Peters
  • Patent number: 7707600
    Abstract: In an interactive broadcasting system, television programming may be broadcast with interleaved web content information. The progress in broadcasting the web content information over one or more transports and over one or more channels within those transports, may be monitored to provide a time based indication of what content has been broadcast. In one embodiment, markers may be inserted into the data transmission flow and a method may be utilized to associate a handle with a particular marker. A method may be called which obtains the handle and another method may be utilized to invoke the handle to obtain current information about broadcast transmissions. This information may be used within a broadcast encoder or may be provided to a content provider, for example, through a log-in server.
    Type: Grant
    Filed: August 21, 1998
    Date of Patent: April 27, 2010
    Assignee: Intel Corporation
    Inventor: Ramanathan Ramanathan
  • Patent number: 7707586
    Abstract: Described is a computing platform comprising a host processing system to host an operating system, a communication adapter to transmit data to or and receive data from a data transmission medium, and a non-volatile storage. The computing platform may also comprise an agent executable independently of the operating system to enable read-only or read/write access to at least a portion of the non-volatile storage.
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: April 27, 2010
    Assignee: Intel Corporation
    Inventors: Carey W. Smith, Howard C Herbert
  • Patent number: 7706248
    Abstract: Embodiments of System and Method for compensating for time-of-arrival differences between uplink packets in a Wireless Network are generally described herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: April 27, 2010
    Assignee: Intel Corporation
    Inventors: Lakshmipathi Sondur, Ashim Biswas, Atanu Guchhait
  • Patent number: 7704791
    Abstract: According to one aspect of the invention, a method of constructing an electronic assembly is provided. A layer of metal is formed on a backside of a semiconductor wafer having integrated formed thereon. Then, a porous layer is formed on the metal layer. A barrier layer of the porous layer at the bottom of the pores is thinned down. Then, a catalyst is deposited at the bottom of the pores. Carbon nanotubes are then grown in the pores. Another layer of metal is then formed over the porous layer and the carbon nanotubes. The semiconductor wafer is then separated into microelectronic dies. The dies are bonded to a semiconductor substrate, a heat spreader is placed on top of the die, and a semiconductor package resulting from such assembly is sealed. A thermal interface is formed on the top of the heat spreader. Then a heat sink is placed on top of the thermal interface.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: April 27, 2010
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Thomas S. Dory
  • Patent number: 7705684
    Abstract: An integrated CMOS power amplifier system to improve amplifier performance, the integrated CMOS power amplifier system including a plurality of differential main amplifier cores, a plurality of ground pads, and a plurality of routes to connect the plurality of differential main amplifier cores to the plurality of ground pads. Each differential main amplifier core includes a pair of collocated main amplifier core transistors. Each ground pad is connected to a subset of the differential main amplifier cores. Embodiments of the integrated CMOS power amplifier system decrease parasitic inductance to ground and increase the transconductance and amplification of the integrated CMOS power amplifier system, thus improving performance.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: April 27, 2010
    Assignee: Intel Corporation
    Inventors: Offir Degani, Mark Ruberto
  • Patent number: 7707266
    Abstract: A scalable, high-performance interconnect scheme for a multi-threaded, multi-processing system-on-a-chip network processor unit. An apparatus implementing the technique includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and a chassis interconnect that may be controlled to selectively connects a given master to a given target. In one embodiment, the chassis interconnect comprises a plurality of sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus, a pull data bus for target writes, and a push data bus for target reads. Multiplexer circuitry for each of the command bus, pull data bus, and push data bus is employed to selectively connect a given cluster to a given target to enable commands and data to be passed between the given cluster and the given target.
    Type: Grant
    Filed: November 23, 2004
    Date of Patent: April 27, 2010
    Assignee: Intel Corporation
    Inventors: Sridhar Lakshmanamurthy, Mark B. Rosenbluth, Matthew Adiletta, Jeen-Xuan Miin, Bijoy Bose
  • Patent number: 7706399
    Abstract: Access points in wireless networks provide contention free access to stations through polling. Polling frames are transmitted to stations at polling intervals. Stations may transmit polling alignment requests to the access point to request a modification of the polling interval. Virtual polling is provided by publishing a virtual polling schedule. Stations respond to the virtual polling schedule without receiving polling frames. Polling intervals used during virtual polling may be modified in response to polling alignment requests from mobile stations.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: April 27, 2010
    Assignee: Intel Corporation
    Inventor: Tomasz Janczak
  • Publication number: 20100100790
    Abstract: A method and apparatus are disclosed that include encoding a codeword using a systematic low density parity check matrix using an encoder, the low density parity check matrix comprising a first sub-matrix associated with information symbols, a second sub-matrix having a block triangular structure associated with a first subset of parity check symbols and a third sub-matrix that is invertible and associated with a second subset of parity check symbols, the encoding performed over the second sub-matrix before the third sub-matrix.
    Type: Application
    Filed: July 6, 2009
    Publication date: April 22, 2010
    Applicant: INTEL CORPORATION
    Inventor: Ilan Sutskover
  • Patent number: 7699210
    Abstract: In some example embodiments, a method includes engaging a first contact on a motherboard with a second contact on an electronic package. A portion of one of the first and second contacts is covered with an interlayer that has a lower melting temperature than both of the first and second contacts. The method further includes bonding the first contact to the second contact by melting the interlayer to diffuse the interlayer into the first and second contacts. The bonded first and second contacts have a higher melting temperature than the interlayer before melting. In other example embodiments, an electronic assembly includes a motherboard having a first contact that is bonded to a second contact on an electronic package. An interlayer is diffused within the first and second contacts such that they have a higher melting temperature than the interlayer before the interlayer is diffused into the first and second contacts.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventor: Daewoong Suh
  • Patent number: 7703126
    Abstract: A method that includes initiating a network access request from an access requester on a platform that couples to a network, the network access request made to a policy decision point for the network. The method also includes establishing a secure communication channel over a communication link between the policy decision point and a policy enforcement point on the platform. Another secure communication channel is established over another communication link. The other communication link is between at least the policy enforcement point and a manageability engine resident on the platform. The manageability engine forwards posture information associated with the access requester via the other secure communication channel. The posture information is then forwarded to the policy decision point via the secure communication channel between the policy enforcement point and the policy decision point.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventors: Hormuzd Khosravi, David Durham, Karanvir Grewal
  • Patent number: 7702856
    Abstract: The prefetch distance to be used by a prefetch instruction may not always be correctly calculated using compile-time information. In one embodiment, the present invention generates prefetch distance calculation code to dynamically calculate a prefetch distance used by a prefetch instruction at run-time.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventors: Rakesh Krishnaiyer, Somnath Ghosh, Abhay Kanhere
  • Patent number: 7700943
    Abstract: An embodiment of the present invention is a technique to functionalize carbon nanotubes in situ. A carbon nanotube (NT) array is grown or deposited on a substrate. The NT array is functionalized in situ with a polymer by partial thermal degradation of the polymer to form a NT structure. The functionalization of the NT structure is characterized. The functionalized NT structure is processed according to the characterized functionalization.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventors: Nachiket R. Raravikar, James C. Matayabas, Jr.
  • Patent number: 7701069
    Abstract: A ball grid array device includes a substrate, further including a first major surface and a second major surface. An array of pads is positioned on one of the first major surface or the second major surface. At least some of the pads include a barrier layer having pores or openings therein. When solder is placed on the pad, the barrier layer forms an intermetallic compound at a rate different from the rate of the intermetallic compound formed between the pad and the solder. The result is a solder ball on a pad that has a first intermetallic compound and a second intermetallic compound.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventors: Kum Foo Leong, Siew Fong Tai, Chee Key Chung
  • Patent number: 7702874
    Abstract: A memory device may determine its device ID in response to the order of a received training pattern. The training pattern may be transmitted over swizzled signal lines to multiple memory devices arranged in a logical stack. Each memory device may be packaged on a substrate having the swizzled signal lines. The memory devices may be physically stacked or planar. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 22, 2005
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventor: Pete D. Vogt
  • Patent number: 7703118
    Abstract: Delivery of feedback information to a scheduling service to determine optimum broadcast times based upon client platform tuner contention is described. A usage pattern of an electronic media device is recorded. The usage pattern is communicated to a scheduling server. Media content is received during a time period selected by the scheduling server based upon the usage pattern.
    Type: Grant
    Filed: September 13, 2001
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventor: John W. Hudspeth
  • Patent number: 7702966
    Abstract: A method for managing a system includes monitoring a plurality of applications running in the system for errors. A prediction is made as to whether errors detected would result in a failure. Fault recovery is initiated in response to a failure prediction. According to one aspect of the present invention, monitoring the plurality of applications includes reading error recorders associated with error occurrence. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 7, 2005
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventors: Neelam Chandwani, Udayan Mukherjee, Chetan Hiremath, Rakesh Dodeja
  • Patent number: 7702333
    Abstract: Embodiments of an authorization server and method for securely reserving resources in a wireless network are generally described herein. Other embodiments may be described and claimed. In some embodiments, access points reserve bandwidth thereon through the verification of reservation tokens received from the mobile station.
    Type: Grant
    Filed: May 11, 2006
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventors: Jesse R. Walker, Kapil Sood, Meiyuan Zhao
  • Patent number: 7702941
    Abstract: According to one embodiment of the present invention, a novel apparatus is disclosed. The apparatus includes an analog to digital converter to receive a predefined synchronization signal and a receiver clock; and an interpolation module coupled to the analog to digital converter to receive an output of the analog to digital converter and to continuously estimate and adapt current delay and skew estimates to synchronize a signal.
    Type: Grant
    Filed: August 13, 2003
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventors: Rainer W. Lienhart, Igor V. Kozintsev
  • Patent number: 7702825
    Abstract: Some embodiments of the invention include apparatus, systems, and methods to perform universal serial bus (USB) suspend and resume operations based on active communication between USB devices to improve power management. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventor: John S. Howard
  • Patent number: 7701973
    Abstract: Provided are techniques for processing a data segment by stripping a header from a transport layer segment, performing protocol data unit detection to determine data for a protocol segment that is part of the transport layer segment data, and performing marker validation and stripping.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventors: Nicholas A. Colman, Ramesh S. Krishnan, Anshuman Thakur, Robert Cone, Daniel A. Manseau
  • Patent number: 7702049
    Abstract: An apparatus and a system, as well as a method and article, may operate to shift a center frequency of selected ones of a plurality of received signals by selected amounts to provide a plurality of shifted signals located in a frequency domain, which may then be combined into a composite signal centered at a selected frequency.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventors: Ernest Tsui, Qinghua Li
  • Patent number: 7703094
    Abstract: A method and apparatus for adaptive and dynamic filtering of threaded programs. An embodiment of a method comprises analyzing the operation of a computer program, the computer program comprising a plurality of program threads; tracking overhead for the computer program; observing program events for the computer program; rationing overhead between program threads in inter-thread program events; and filtering program events based on a dynamic threshold.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventors: Ekarat T Mongkolsmai, Douglas R Armstrong, Sanjiv M Shah
  • Patent number: 7702298
    Abstract: Methods and apparatuses, including computer program products, for spatial processing in a radio receiver. One embodiment is a radio receiver for operation in a wireless communication system. The radio receiver may include a receive processing unit to process signals received by an antenna array by applying a selected spatial processing mode of a plurality of spatial processing modes. The modes include one or more modes of one or more spatial processing methods. The receiver also includes a selector to select the spatial processing mode from the plurality of spatial processing modes. The selecting includes selecting the spatial processing method in the case that the set of spatial processing modes are of more than one spatial processing method.
    Type: Grant
    Filed: September 12, 2007
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventors: Craig H. Barratt, Athanasios A. Kasapi
  • Patent number: 7703088
    Abstract: Selected regions of native instructions translated in a DBT environment from non-native instructions are compressed based on the independent compression of different fields of selected instructions using compression tables to reduce a length of selected fields. The regions of compressed instructions are stored and de-compressed into the native instructions during subsequent execution using de-compression tables. Specifically, for native instructions of a selected region, selected types of opcodes and/or operands may be compressed independently. The types may be selected by profiling the opcodes using benchmark programs and creating an opcode conversion table prior to compression, and scanning of the operands and creating an operand conversion table during compression of the opcodes.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventors: Zhiyuan Li, Youfeng Wu
  • Patent number: 7702352
    Abstract: Network node power management methods and apparatus are generally described herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: May 13, 2005
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventors: W. Steven Conner, Luiyang Lily Yang
  • Patent number: 7702336
    Abstract: Channels are assigned based on co-spatial constraints in wireless network using spatial division multiple access. In one example, the invention includes assigning a co-spatial constraint to each of a plurality of conventional traffic communications channels of a base station, and receiving a request from a user terminal to communicate using a traffic communication channel of the base station. The invention further includes measuring a quality parameter of the request deriving a co-spatial constraint for the user terminal, assigning the user terminal co-spatial constraint to the user terminal, and assigning the user terminal to a traffic communication channels having a channel co-spatial constraint that is no less than the user terminal co-spatial constraint and that has no more assigned radios than permitted by the channel co-spatial constraint.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventors: Elvino S. Sousa, Athanasios A. Kasapi, Mitchell D. Trott
  • Patent number: 7701238
    Abstract: In one embodiment, the present invention includes a burn-socket for insertion into a test board, where the burn-in socket is coupled to receive a semiconductor device under test (DUT). The burn-in socket includes a substrate to support the semiconductor DUT, which includes a heating element embedded in a layer of the substrate. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventors: Anthony Yeh Chiing Wong, Victor Henckel, Boon Liang Heng, Christopher Wade Ackerman, James C. Shipley
  • Patent number: 7701913
    Abstract: Embodiments of methods and apparatus for providing a platform coexistence system of multiple wireless communication devices are generally described herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventors: Camille Chen, Gedon Rosner, Boris Ginzburg
  • Patent number: 7702883
    Abstract: A variable-width memory may comprise multiple memory banks from which data may be selectively read in such a way that overall memory access requirements may be reduced, which may result in associated reduction in power consumption.
    Type: Grant
    Filed: May 5, 2005
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventors: Jian Lin, Anthony L. Chun
  • Patent number: 7702826
    Abstract: An apparatus and method related to performing Remote Direct Memory Access Request (“RDMA”) is presented. In one embodiment, the apparatus comprises Remote direct memory access (“RDMA”) logic that executes a direct memory access (“DMA”) request from the remote peer. The apparatus further comprising a protection checking logic to verify a key and a target address in the DMA request and conversion logic to convert the target address to an input/output virtual address (“IOVA”) if the conversion is required. The IOVA is to be translated to the host physical address by an address translation unit at another hardware subsystem.
    Type: Grant
    Filed: December 28, 2005
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventors: Ali S. Oztaskin, Rajesh S. Madukkarumukumana, Greg J. Regnier
  • Patent number: 7700470
    Abstract: Embodiments of an apparatus and methods for providing a workfunction metal gate electrode on a substrate with doped metal oxide semiconductor structures are generally described herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Uday Shah, Jack T. Kavalieros, Brian S. Doyle
  • Patent number: 7700476
    Abstract: A microelectronic assembly and method for fabricating the same are described. In an example, a microelectronic assembly includes a microelectronic device having a surface with one or more areas to receive one or more solder balls, the one or more areas having a surface finish comprising Ni. A solder material comprising Cu, such as flux or paste, is applied to the Ni surface finish and one or more solder balls are coupled to the microelectronic device by a reflow process that forms a solder joint between the one or more solder balls, the solder material comprising Cu, and the one or more areas having a surface finish comprising Ni.
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventors: Daewoong Suh, Stephen E. Lehman, Jr., Mukul Renavikar
  • Patent number: 7700246
    Abstract: A conductive photolithographic film and method of forming a device using the conductive photolithographic film. The method includes depositing a conductive photolithographic film on a top surface of a substrate; and patterning the conductive photolithographic film to create a desired circuit pattern using a lithographic process. The conductive photolithographic film comprising about 50% to about 60% of a mixture of epoxy acrylate, a thermal curing agent, and a conductive polymer; about 20% to about 30% of a lithographic reactive component; about 10% to about 15% of a photo-active material; and about 3% to about 5% of additives that enhance conductivity of the conductive photolithographic polymer.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventors: Rebecca Shia, Jack Tsung-Yu Chen
  • Patent number: 7700975
    Abstract: Metal-Semiconductor-Metal (“MSM”) photodetectors and methods to fabricate thereof are described. The MSM photodetector includes a thin heavily doped (“delta doped”) layer deposited at an interface between metal contacts and a semiconductor layer to reduce a dark current of the MSM photodetector. In one embodiment, the semiconductor layer is an intrinsic semiconductor layer. In one embodiment, the thickness of the delta doped layer is less than 100 nanometers. In one embodiment, the delta doped layer has a dopant concentration of at least 1×1018 cm?3. A delta doped layer is formed on portions of a semiconductor layer over a substrate. Metal contacts are formed on the delta doped layer. A buffer layer may be formed between the substrate and the semiconductor layer. In one embodiment, the substrate includes silicon, and the semiconductor layer includes germanium.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventors: Titash Rakshit, Miriam Reshotko
  • Patent number: 7703138
    Abstract: Provided are techniques for monitoring communication packets. A communication packet is received. A communication packet signature of the communication packet is determined. The communication packet signature is compared to one or more site-specific application signatures. In response to determining that the communication packet signature matches at least of the one or more site-specific application signatures, it is determined that the communication packet is to be trusted.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventors: Nehal G. Desai, Patrick J. Chauvin, Jac M. Noel
  • Patent number: 7702981
    Abstract: A boundary scan technique to generate toggling waveform such as a square wave signal to perform structural testing is disclosed. An instr_extesttoggle command is provided that enables IEEE 1149.1 boundary scan cell to selectively generate the toggling signal on the pre-specified output pads of the integrated circuit. The frequency of the toggling signal may be controlled by the JTAG clock signal and the frequency of the toggling signal may be independent of the length of the boundary scan chain. Such an approach circumvents provisioning test points on the interconnects of a printed circuit board.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventors: James Grealish, Dave F. Dubberke, Milo J. Juenemann, Christopher J. Koza, Eric T. Fought
  • Patent number: 7700945
    Abstract: An integrated circuit (IC) die includes a plurality of edge counters. Each edge counter is provided to detect at least one change in signal level at a respective location on the IC die. The IC die is in communication with a memory and also includes an event recording circuit on the IC die provided to store states of the counters in the memory.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventors: Pat Brouillette, Jason G. Sandri
  • Patent number: 7697959
    Abstract: In a communication device compatible with either a SISO or MIMO access point, a set of antennas is configured as either sector-directional or omni-directional, depending upon whether the communication channel is characterized by the communication device as either strongly line of sight, or strongly scattering, respectively. In some embodiments, for the case in which a MIMO access point is utilized, the singular values of an estimated channel matrix are generated, and based upon the singular values, the characteristics of the communication channel is estimated. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 10, 2006
    Date of Patent: April 13, 2010
    Assignee: Intel Corporation
    Inventors: Guoqing Li, Minyoung Park, Liuyang Lily Yang
  • Patent number: 7697691
    Abstract: Delivering a Direct Proof private key to a device installed in a client computer system in the field may be accomplished in a secure manner without requiring significant non-volatile storage in the device. A unique pseudo-random value is generated and stored in the device at manufacturing time. The pseudo-random value is used to generate a symmetric key for encrypting a data structure holding a Direct Proof private key and a private key digest associated with the device. The resulting encrypted data structure is stored on a protected on-liner server accessible by the client computer system. When the device is initialized on the client computer system, the system checks if a localized encrypted data structure is present in the system. If not, the system obtains the associated encrypted data structure from the protected on-line server using a secure protocol.
    Type: Grant
    Filed: July 14, 2004
    Date of Patent: April 13, 2010
    Assignee: Intel Corporation
    Inventors: James A. Sutton, II, Ernie F. Brickell, Clifford D. Hall, David W. Grawrock
  • Patent number: 7698512
    Abstract: In one embodiment, the present invention includes a method for determining if data of a memory request by a first agent is in a memory region represented by a region indicator of a region table of the first agent, and transmitting a compressed address for the memory request to other agents of a system if the memory region is represented by the region indicator, otherwise transmitting a full address. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: April 13, 2010
    Assignee: Intel Corporation
    Inventors: Grigorios Magklis, Jose Gonzalez, Pedro Chaparro, Qiong Cai, Antonio Gonzalez
  • Patent number: 7698584
    Abstract: A method, apparatus and system to enable a data processing device to operate while seemingly “off”. According to one embodiment, a data processing device is configured to recognize a new system state, i.e., Visual Off. On such a data processing device, when the power button is pressed, the request to turn off the device is intercepted by a module and the device is transitioned to a Visual Off state. To the user, this transition appears instantaneous. During the transition, audible and visual indicators on the data processing device and on human interactive devices (“HID devices”) coupled to the data processing device may be turned off and/or disabled. While in the Visual Off state, the device may be fully operational, or in an alternate embodiment, the device may be placed in a low power state. When the user presses the power button again to “wake up” the data processing device, the device may transition from Visual Off into an “on” state (“Visual On”), i.e.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: April 13, 2010
    Assignee: Intel Corporation
    Inventors: Robert A. Dunstan, Dan H. Nowlin, Clifton W. Laney
  • Patent number: 7698507
    Abstract: A computing system may comprise a processor and a memory controller hub coupled by an external bus such as the front side bus. The processor may also comprise a cache. The processor may operate in SMM and the memory coupled to the memory controller hub may comprise SMM spaces such as compatible, HSEG, and TSEG areas. A software-based attack may write malicious instructions into the cache at an address corresponding to the SMM spaces. The illegal processor memory accesses that occur entirely inside the processor caches due to the cache attack may be forced to occur on the external bus. The memory controller hub may be capable of handling the memory accesses occurring on the external bus thus, protecting the SMM spaces against cache attack.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: April 13, 2010
    Assignee: Intel Corporation
    Inventor: Sergiu D. Ghetie
  • Patent number: 7697601
    Abstract: In some embodiments, equalizer circuits with controllably variable offsets at their outputs are provided.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: April 13, 2010
    Assignee: Intel Corporation
    Inventors: Mozhgan Mansuri, Frank O'Mahony, Bryan K. Casper, James E. Jaussi
  • Patent number: 7698575
    Abstract: A processor is provided with a workload that has a real-time demand. A processor clock frequency requirement is set for the processor, based on a deadline margin for the real-time demand. Other embodiments are also described and claimed.
    Type: Grant
    Filed: March 30, 2004
    Date of Patent: April 13, 2010
    Assignee: Intel Corporation
    Inventor: Eric C. Samson
  • Patent number: 7697906
    Abstract: Embodiments of apparatuses, articles, methods, and systems for predicting one or more performance metrics for an over-the-air link in the presence of co-channel interference are generally described herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: April 13, 2010
    Assignee: Intel Corporation
    Inventors: Nageen Himayat, Roopsha Samanta, Shilpa Talwar
  • Patent number: 7698487
    Abstract: Methods and systems for a low-cost high density compute environment with increased fail-over support through resource sharing and resources chaining. In one embodiment, one of a number of servers qualified to share resources is elected as a resource server. The shared resource can be firmware memory, hard-drive, co-processor, etc. The elected server responds to requests from individual requesters and provides the responses, such as firmware images. In one embodiment, all the blade servers on a rack use an image server for their firmware image so that these blade servers can automatically adopt a common personality across the entire rack. If the elected image server fails, a dynamic process elects an alternate image server. In one embodiment, among a set of qualified servers, only one is actively elected at a given time.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: April 13, 2010
    Assignee: Intel Corporation
    Inventors: Michael A. Rothman, Vincent J. Zimmer, Gregory P. McGrath
  • Patent number: 7697694
    Abstract: Methods and apparatuses for synchronizing the exchange of cryptography information between kernel drivers. A high level application in an electronic system passes a pointer to a base driver. The pointer is a unique identifier for cryptography information, such as a Security Association (SA), that the base driver uses to populate a cryptography information table for performing cryptography operations on secure traffic data packets. If the network interface device and/or its associated driver are reset, the pointer is used to repopulate the cryptography information table with specific cryptography information needed to perform cryptography operations on the data packets.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: April 13, 2010
    Assignee: Intel Corporation
    Inventors: Moshe Valenci, Linden Minnick
  • Patent number: 7698527
    Abstract: A motherboard may be adapted to selectively implement one of two different memory technologies. For example, the motherboard may be able to subsequently implement a subsequently developed memory technology. In some embodiments, the motherboard is capable of detecting whether a memory module is in a slot dedicated to a first or a second memory technology and, based on the presence of a memory module in an appropriate slot, the motherboard may be adapted to operate with the particular, selected memory technology.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: April 13, 2010
    Assignee: Intel Corporation
    Inventors: Terence Chin Kee Meng, Yong Yean Sun, Ng Kay Ming
  • Patent number: RE41217
    Abstract: A method, apparatus, and system for controlling the voltage levels across capacitors coupled between a first node and a second node of an integrated circuit so that the voltage levels across these capacitors will not exceed the breakdown voltage limitation of these capacitors. The voltage level between the first and second nodes of the integrated circuit can vary from a second voltage level to a first voltage level when the integrated circuit transitions from a second power state to a first power state, respectively. A first capacitor and a second capacitor are connected in series between the first and second nodes of the integrated circuit forming a middle node between the first and second capacitors.
    Type: Grant
    Filed: October 2, 2003
    Date of Patent: April 13, 2010
    Assignee: Intel Corporation
    Inventors: Ramkarthik Ganesan, Owen W. Jungroth