Patents Examined by A. Decady
  • Patent number: 11863317
    Abstract: Data can be sent from a sender to a receiver with reliability of transmission encoding data blocks into packets each having a packet header and a packet payload, a block size, a global packet sequence number that uniquely identifies the packet relative to other packets of the data, a block identifier of the data block, and an encoding identifier. The sender determines from feedback from the receiver whether packets are lost and sends repair packets as needed.
    Type: Grant
    Filed: August 19, 2022
    Date of Patent: January 2, 2024
    Assignee: BitRipple, Inc.
    Inventors: Michael George Luby, Lorenz Christoph Minder
  • Patent number: 11862271
    Abstract: Various implementations described herein refer to a device having an encoder coupled to memory. The ECC encoder receives input data from memory built-in self-test circuitry, generates encoded data by encoding the input data and by adding check bits to the input data, and writes the encoded data to memory. The device may have an ECC decoder coupled to memory. The ECC decoder reads the encoded data from memory, generates corrected data by decoding the encoded data and by extracting the check bits from the encoded data, and provides the corrected data and double-bit error flag as output. The ECC decoder has error correction logic that performs error correction on the decoded data based on the check bits, wherein if the error correction logic detects a multi-bit error in the decoded data, the error correction logic corrects the multi-bit error in the decoded data to provide the corrected data.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: January 2, 2024
    Assignee: Arm Limited
    Inventors: Andy Wangkun Chen, Yannis Jallamion-Grive, Cyrille Nicolas Dray
  • Patent number: 11863328
    Abstract: Packet recovery mechanisms for wireless networks, which improve end-to-end (e2e) reliability, are provided. First embodiments include packet retransmission between a receiver and a transmitter, wherein, if the transmitter cannot find a lost packet in its transmission buffer, the transmitter sends a First Sequence Number (FSN) report to the receiver to notify the receiver of a sequence number (SN) of an oldest (acknowledged) packet in the buffer. In response, the receiver does not report lost packets whose SN is older than the FSN. Second embodiments involve using a network coding algorithm to recover lost packets, wherein the transmitter sends a control message to the receiver that includes a coded packet to be recovered and information for decoding the coded packet. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: January 2, 2024
    Assignee: Intel Corporation
    Inventors: Jing Zhu, Pengfei Zhao, Nageen Himayat, Vered Bar Bracha
  • Patent number: 11863318
    Abstract: In one embodiment, a method is provided. The method includes receiving a request for a first set of data stored on a data storage system from a computing device. The method also includes retrieving the first set of data from a data storage device of the data storage system. The method further includes generating a set of codewords based on the first set of data and an error correction code. The method further includes transmitting a set of network packets to the computing device. Each network packet of the set of network packets comprises a codeword from the set of codewords.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: January 2, 2024
    Assignee: FRONTIIR PTE LTD.
    Inventors: Changbin Liu, Boon Thau Loo
  • Patent number: 11853157
    Abstract: An address fault detection system includes write and read access circuits and a fault management circuit. The write access circuit receives an address and reference data for a write operation associated with a memory and parity data generated based on the reference data, and writes the reference data and the parity data to first and second memory blocks of the memory, respectively. The read access circuit receives the same address for a read operation associated with the memory and reads another reference data and another parity data from the first and second memory blocks, respectively. The fault management circuit compares the read parity data with parity data generated based on the read reference data to detect an address fault in the memory. The written and read reference data are different when the address fault is detected, and same when the address fault is not detected.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: December 26, 2023
    Assignee: NXP B.V.
    Inventors: Arvind Kaushik, Aarul Jain, Nishant Jain
  • Patent number: 11855780
    Abstract: Various aspects related to ACK/NACK feedback for multi-TRP transmission scenarios are described. A base station, may send, to a UE, information indicating PDCCH monitoring occasions for each of a plurality of TRPs. In one aspect, the base station may send information indicating whether ACK/NACK feedback across the plurality of TRPs is allowed. The base station may send rules to the UE for performing ACK/NACK feedback bundling for providing feedback to the plurality of TRPs. The base station may also send information indicating a DAI definition for interpreting DAIs transmitted by the plurality of TRPs in corresponding PDCCH transmissions indicating whether the DAIs are independent or joint. The base station may receive a joint ACK/NACK feedback from the UE in a PUCCH based on the rules, or may receive multiple ACK/NACK feedback from the UE in a PUCCH for a first TRP independent from a second TRP.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: December 26, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Xiaoxia Zhang, Jing Sun, Tamer Kadous
  • Patent number: 11855778
    Abstract: A network interface for a storage controller includes a processor and a memory that stores an instruction code to be executed by the processor. The processor executes protocol processing for transmitting and receiving packets via a network. The processor reproduces a first packet not received from the network, from a plurality of other received packets included in an error correction packet group same as that of the first packet.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: December 26, 2023
    Assignee: HITACHI, LTD.
    Inventors: Nobuhiro Yokoi, Hiroka Ihara, Akira Deguchi
  • Patent number: 11853159
    Abstract: A fault tolerant quantum error correction protocol is implemented for a surface code comprising Gottesman Kitaev Preskill (GKP) qubits. Analog information is determined when measuring position or momentum shifts, wherein the analog information indicates a closeness of the shift to a decision boundary. The analog information is further used to determine confidence values for error corrected measurements from the GKP qubits of the surface code. These confidence values are used to dynamically determine edge weights in a matching graph used to decode syndrome measurements of the surface code, wherein the confidence values are obtained using a maximum-likelihood decoding protocol for two-qubit gates. Space-time correlated edges and other edges are included in the matching graph and weighted based at least in part on confidence values for qubits forming the respective edges.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: December 26, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Christopher Chamberland, Kyungjoo Noh, Fernando Brandao
  • Patent number: 11843458
    Abstract: A control device for use in a broadcast system includes a broadcast controller that controls a broadcast transmitter of the broadcast system that broadcasts broadcast signals in a coverage area for reception by terminals including a broadcast receiver and a broadband receiver, and a broadband controller that controls a broadband server of a broadband system that provides redundancy data to terminals within the coverage area. The broadband controller is configured to control the provision of redundancy data by the broadband server for use by one or more terminals which use the redundancy data together with broadcast signals received via said broadcast system for recovering content received within the broadcast signals and/or provided via the broadband system.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: December 12, 2023
    Assignee: SATURN LICENSING LLC
    Inventors: Junge Qi, Joerg Robert, Jan Zoellner, Lothar Stadelmeier, Nabil Loghin
  • Patent number: 11842782
    Abstract: Phased parameterized combinatoric testing for a data storage system is disclosed. A testing recipe can be performed according to different input arguments. Combinatoric testing of the data storage system can be based on different combinations of operations and arguments. The disclosed testing can employ a consistent integer index for arguments passed into the sequenced operations of the recipe. The recipe can be employed to generate a phased test tree that can enable testing based on a phase rather than loading an entire test suite into memory. The consistent integer index can be used to identify failed test cases such that the entire test can be reconstituted from stored failed test information. Distribution of test cases to worker process can based on the phased test tree to facilitate interning an operation. Stored failed test information can include human-readable failure information.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: December 12, 2023
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventor: Matthew Bryan
  • Patent number: 11831330
    Abstract: A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: November 28, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-ho Myung, Belkacem Mouhouche, Daniel Ansorregui Lobete, Kyung-joong Kim, Hong-sil Jeong
  • Patent number: 11824558
    Abstract: An encoding apparatus is provided. The encoding includes a low density parity check (LDPC) encoder which performs LDPC encoding on input bits based on a parity-check matrix to generate an LDPC codeword formed of 64,800 bits, in which the parity-check matrix includes an information word sub-matrix and a parity sub-matrix, the information word sub-matrix is formed of a group of a plurality of column blocks each including 360 columns, and the parity-check matrix and the information word sub-matrix are defined by various tables which represent positions of value one (1) present in every 360-th column.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: November 21, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-sil Jeong, Se-ho Myung, Kyung-joong Kim
  • Patent number: 11816353
    Abstract: Technology is disclosed herein for managing parity data in non-volatile memory. As user data is programming into respective groups of non-volatile memory cells, the system accumulates parity data. The system may accumulate XOR parity based on successive bitwise XOR operations of user data. After programming is complete, the system performs a post-program read test of the data stored into each respective group of memory cells. The system re-calculates the parity data such that the parity data is no longer based on the user data that was stored in any group of memory cells for which the post-program read test failed. For example, the system will perform an additional bitwise XOR between the accumulated XOR parity data with the user data that was stored in the group of memory cells for which the post-program read test failed. The parity data is programmed to a group of memory cells.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: November 14, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventor: Varun Sharma
  • Patent number: 11818073
    Abstract: Methods, apparatus, systems and procedures to manage a multicast communication to a multicast group implemented by a respective wireless transmit/receive unit (WTRU) of WTRUs in the multicast group are disclosed. One representative method includes receiving, by the respective WTRU of the multicast group, a configuration, the configuration indicating a Random Access Channel (RACH) preamble to use for a negative acknowledgement (NACK) response to a multicast transmission to the respective WTRU, monitoring, by the respective WTRU, for data of the multicast transmission, determining, by the respective WTRU, whether the monitored for data was successfully received; and on condition that the monitored for data was not successfully received, sending, by the respective WTRU, the RACH preamble indicated by the received configuration.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: November 14, 2023
    Assignee: InterDigital Patent Holdings, Inc.
    Inventors: Janet A Stern-Berkowitz, Moon-il Lee
  • Patent number: 11817952
    Abstract: A system for providing end-to-end data protection between a transmitting end device and a receiving end device is presented. The system has a transmitting end device to calculate a first check value for a first message, which has first and second data blocks; the receiving end device; and a remapping device. The remapping device is configured to remap a data block among the first and second data blocks for generating a second message for the receiving end device. The remapping device also determines a remapping value based on the data block and the remapped data block, such that a second check value that would be calculated for the second message would be equal to the first check value, and wherein the second message comprises the other one of the first and second data blocks, the remapped data block, and the remapping value.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: November 14, 2023
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Carl Adams-Waite, Robert Waterworth
  • Patent number: 11809273
    Abstract: The present invention provides a method for detecting a flash memory module and an associated SoC. The method reads data in a flash memory module with a specific data format, and then determining a plurality of characteristic parameters of the flash memory module and a size of a page by decoding and checking the data. Therefore, the SoC does not need to design a one-time-programmable memory or strap pins, so as to reduce the manufacturing cost of the SoC.
    Type: Grant
    Filed: April 1, 2022
    Date of Patent: November 7, 2023
    Assignee: Realtek Semiconductor Corp.
    Inventors: Jia-Jhe Li, Chia-Liang Hung
  • Patent number: 11811424
    Abstract: Methods, systems, and devices for fixed weight codewords for ternary memory cells are described. A memory device may generate a codeword from a set of data bits and invert a portion of the codeword so that the codeword is associated with a target distribution of programmable states. After inverting the portion of the codeword, the memory device store the codeword in a set of ternary cells according to a coding scheme. The memory device may read the codeword from the set of ternary cells and select one or more reference voltages for the set of ternary cells based on the target distribution for the codeword and the states of the ternary cells.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: November 7, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Christophe Vincent Antoine Laurent, Riccardo Muzzetto
  • Patent number: 11803441
    Abstract: Techniques regarding calibrating one or more quantum decoder algorithms are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a correlation inversion decoder component that can calibrate a quantum decoder algorithm for decoding a quantum error-correcting code by estimating hyperedge probabilities of a decoding hypergraph that are consistent with a syndrome dataset.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: October 31, 2023
    Assignee: International Business Machines Corporation
    Inventors: Edward Hong Chen, Andrew W. Cross, Youngseok Kim, Neereja Sundaresan, Maika Takita, Antonio Corcoles-Gonzalez, Theodore James Yoder
  • Patent number: 11797380
    Abstract: Methods, systems, and devices for host-configurable error protection are described. A host system may receive an indication of a set of logical addresses supported by the memory system and available for use by the host system. The host system may divide the set of logical addresses into subsets of logical addresses. Each subset of logical addresses may be associated with a different type of data. The host system may determine an error protection configuration for a subset of logical addresses based at least in part on the type of data associated with the subset of logical addresses. The host system may then send to the memory system an indication of the subset of logical addresses and an indication of the error protection configuration for the subset of logical addresses.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: October 24, 2023
    Assignee: Micron Technology, Inc.
    Inventors: David Aaron Palmer, Jonathan S. Parry
  • Patent number: 11799611
    Abstract: Methods, systems, and devices for wireless communication are described. A wireless device may transmit feedback, such as hybrid automatic repeat request (HARD) feedback for groups of code blocks rather than for an entire transport block or individual code blocks. The wireless device may transmit an acknowledgement (ACK) or negative-acknowledgement (NACK) to provide feedback for each code block group of a set of code block groups. An ACK may indicate that code blocks in a code block group were successfully decoded, and a NACK may indicate that at least one code block in a code block group was not successfully decoded. Wireless devices may support several techniques for grouping code blocks for feedback reporting to allow for efficient retransmissions and limited overhead. Different grouping schemes may be employed depending on system constraints, device capability, link conditions, or the like.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: October 24, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Jay Kumar Sundararajan, Renqiu Wang, Hao Xu, Naga Bhushan, Haitong Sun, Wanshi Chen