Abstract: A memory device including a memory cell array, a redundant fuse circuit and a memory controller is provided. The memory cell array includes multiple regular memory blocks and multiple redundant memory blocks. The redundant fuse circuit includes multiple fuse groups recording multiple repair information. Each repair information is associated with a corresponding one of the redundant memory blocks and includes a repair address, a first enable bit, and a second enable bit. The memory controller includes multiple determining circuits. Each of the multiple determining circuits generates a hit signal according to an operation address, the repair address, the first enable bit, and the second enable bit. When a target memory block is bad, and the determining circuit of the memory controller generates the hit signal, the memory controller disables the redundant memory block that is bad according to the hit signal.

Abstract: Apparatuses and methods for extracting ordered data sub-components from a data item are disclosed. A received data item has a data structure to accommodate multiple data sub-components. The data item indicates which data sub-components are valid. Adders sum respective subsets of indications of the valid data sub-component positions, with each adder covering one more position than the previous adder. Transitions of the counts generated by the respective adders are used to determine the ordinal valid data sub-component positions in the data item, which can then be output on the basis of the data item and the identified transition positions. Without requiring feedback paths from an identified earlier ordinal position to identify a later ordinal position, the set of ordered data sub-components can be extracted more quickly.

Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.

Abstract: In one form, a memory controller includes a command queue, an arbiter, and a replay queue. The command queue receives and stores memory access requests. The arbiter is coupled to the command queue for providing a sequence of memory commands to a memory channel. The replay queue stores the sequence of memory commands to the memory channel, and continues to store memory access commands that have not yet received responses from the memory channel. When a response indicates a completion of a corresponding memory command without any error, the replay queue removes the corresponding memory command without taking further action. When a response indicates a completion of the corresponding memory command with an error, the replay queue replays at least the corresponding memory command. In another form, a data processing system includes the memory controller, a memory accessing agent, and a memory system to which the memory controller is coupled.

Abstract: An encoder receives a concatenated encoder input block d, splits d into an outer code input array a, and encodes a using outer codes to generate an outer code output array b. The encoder generates, from b, a concatenated code output array x using a layered polarization adjusted convolutional (LPAC) code. A decoder counts layers and carries out an inner decoding operation for a layered polarization adjusted convolutional (LPAC) code to generate an inner decoder decision {tilde over (b)}i from a concatenated decoder input array y and a cumulative decision feedback ({circumflex over (b)}1, {circumflex over (b)}2, . . . , {circumflex over (b)}i?1).

Abstract: A method for enhanced error protection using double-cyclic redundancy check (CRC) includes receiving a first packet, by a first physical layer (PHY). The first packet includes a source packet and a first CRC. The method also includes encrypting the first packet having the first CRC to generate an encrypted first packet. The method further includes appending a second CRC to the encrypted first packet to produce a second packet, and transmitting the second packet to a second PHY via a transmission line.

Abstract: A method of managing a non-volatile memory includes during a data writing process, selecting, by a program triggering the data writing process, an error detection and correction code from among two codes depending on a type of information being written. The information is written into the non-volatile memory, where the information is associated with the selected error detection and correction code.

Abstract: A crossing frames encoding management method, a memory storage apparatus, and a memory control circuit unit are disclosed. The method includes: reading a tag swap information corresponding to a first physical group; encoding a first data; storing a first part of the encoded first data to at least one first physical unit corresponding to a first tag information in the first physical group; and storing a second part of the encoded first data to at least one second physical unit corresponding to a second tag information in the first physical group according to the tag swap information. The first tag information corresponds to a first crossing frames encoding group. The second tag information corresponds to a second crossing frames encoding group. The first crossing frames encoding group is different from the second crossing frames encoding group.

Abstract: Systems, methods, and apparatus including computer-readable mediums for determining read voltages for memory systems are provided. In one aspect, a memory system includes a memory storing data and a memory controller coupled to the memory. The memory controller is configured to: obtain a first reading output of target memory data in the memory using a first read voltage, and in response to determining that the first reading output fails to pass an Error-Correcting Code (ECC) test, provide the first read voltage to the memory. The memory is configured to: determine a second read voltage based on the first read voltage and generate a second reading output of the target memory data using the second read voltage.

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, methods, and memories that are capable of performing pattern matching operations within a memory device. The pattern matching operations may be performed on data stored within the memory based on a pattern stored in a register. The result of the pattern matching operation may be provided by the memory. The data may be retrieved from a memory array for the pattern matching operation by a read operation, a refresh operation, an error correction operation, and/or a pattern matching operation. The data may be retrieved from incoming data input lines instead of or in addition to the memory array. How the data is stored or retrieved for pattern matching operations may be controlled by a memory controller.

Abstract: The inventive concept relates to method for encoding and decoding sparse codes and orthogonal sparse superposition codes. A sparse code encoding method which is to be performed by an encoding apparatus, according to an embodiment of the inventive concept may include selecting an index set that is a part of a code block by using an information bit, and mapping a codeword less than a preset size to the selected index set.

Abstract: Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a multiple-name-space testing system comprises a load board, testing electronics, and a namespace testing tracker. The load board is configured to couple with a plurality of devices under test (DUTs). The testing electronics are configured to test the plurality of DUTs, wherein the testing electronics are coupled to the load board. The controller is configured to direct testing of multiple-name-spaces across the plurality of DUTs at least in part in parallel. The controller can be coupled to the testing electronics. The namespace testing tracker is configured to track testing of the plurality of DUTs, including the testing of the multiple-name-spaces across the plurality of DUTs at least in part in parallel. In one embodiment, the DUTs are NVMe SSD devices.

Abstract: In data communications, a suitably designed contrast coding scheme, comprising a process of contrast encoding (108) at a transmitter end (101) and a process of contrast decoding (120) at a receiver end (103), may be used to create contrast between the bit error rates ‘BERs’ experienced by different classes of bits. Contrast coding may be used to tune the BERs experienced by different subsets of bits, relative to each other, to better match a plurality of forward error correction ‘FEC’ schemes (104, 124) used for transmission of information bits (102), which may ultimately provide a communications system (100) having a higher noise tolerance, or greater data capacity, or smaller size, or lower heat.

Abstract: Systems and methods related to memory devices that may perform error check and correct (ECC) functionality. The systems and methods may employ ECC logic that may be shared between two or more banks. The ECC logic may be used to perform memory operations such as read, write, and masked-write operations, and may increase reliability of storage data.

Abstract: A memory system includes a nonvolatile memory which comprises a plurality of memory cells capable of storing 4-bit data represented by first to fourth bits by sixteen threshold regions, and a memory controller configured to cause the nonvolatile memory to execute a first program for writing data of the first bit, the second bit, and the fourth bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit. In fifteen boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions, a maximum value of the number of first boundaries used for determining a value of the data of the first bit, the number of second boundaries used for determining a value of the data of the second bit, the number of third boundaries used for determining a value of the data of the third bit.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.

Abstract: Provided herein are method and apparatus for channel coding in the fifth Generation (5G) New Radio (NR) system. An embodiment provides an apparatus for a Next Generation NodeB (gNB), including circuitry, which is configured to: generate Downlink Control Information (DCI) payload for a NR-Physical Downlink Control Channel (NR-PDCCH); attach Cyclic Redundancy Check (CRC) to the DCI payload; mask the CRC with an Radio Network Temporary Identifier (RNTI) using a bitwise modulus 2 addition operation, wherein the number of bits for the RNTI is different from the number of bits for the CRC; and perform polar encoding for the DCI payload with the masked CRC.

Abstract: Transferring data between memories may include reading data associated with a memory transfer transaction from a first memory, determining whether a bypass indication associated with the memory transfer transaction is asserted, and transferring the data from the first memory to a second memory. The transferring may include bypassing the first-processing if the bypass indication is asserted. The transferring may further include bypassing second-processing the data if the bypass indication is asserted. Following bypassing the second-processing, the data may be stored in the second memory.

Abstract: A memory device includes a plurality of memory die blocks and a plurality of memory channels operably coupled to the plurality of memory die blocks and a memory controller configured to identify one or more memory die blocks as being invalid. The memory controller obtains a first matrix storing a mapping of memory channels to memory die blocks and creates a new mapping of memory channels to memory die blocks excluding the invalid memory die blocks. The new mapping is stored in a second matrix and one or more operations are performed on the memory die blocks based on the new mapping.

Abstract: A method for storing data includes determining, using a first match line, that a match word satisfies a first content addressable memory (CAM) word stored in a CAM array, wherein the CAM array is configured to store a second CAM word that matches the first CAM word. The method further includes determining that a first parity bit associated with the first CAM word matches a first parity of the first CAM word. The method further includes, in response to determining that the first parity bit associated with the first CAM word matches the first parity determining, using the first match line, a first random access memory (RAM) word stored in a RAM array and outputting the first RAM word.