Abstract: Often there are errors when reading data from computer memory. To detect and correct these errors, there are multiple types of error correction codes. Disclosed is an error correction architecture that creates a codeword having a data portion and an error correction code portion. Swizzling rearranges the order of bits and distributes the bits among different codewords. Because the data is redistributed, a potential memory error of up to N contiguous bits, where N for example equals 2 times the number of codewords swizzled together, only affects up to, at most, two bits per swizzled codeword. This keeps the error within the error detecting capabilities of the error correction architecture. Furthermore, this can allow improved error correction and detection without requiring a change to error correcting code generators and checkers.

Abstract: A combined error checker and sequence generator which shares a LFSR is disclosed which reduces complexity, cost, and area required for implementation while also improving timing margin. A clock and data recovery system recovers a data signal received over a channel from a remote transceiver. Control logic selects different modes of operation of the system. An error detector compares the two sequence signals and records errors in response to differences between the two sequence signals. A sequence generator generates a sequence signal for use by the error detector as a reference sequence signal or for transmission to a remote transceiver. The system includes one or more switching elements configured to selectively route the generated sequence as feedback into the sequence generator or the received sequence signal into the sequence generator subject to whether the combined error checker and sequence generator is in error checker mode or sequence generator mode.

Abstract: Certain aspects of the present disclosure provide techniques for performing compute in memory (CIM) computations. A device comprises a CIM module configured to apply a plurality of analog weights to data using multiply-accumulate operations to generate an output. The device further comprises a digital weight storage unit configured to store digital weight references, wherein a digital weight reference corresponds to an analog weight of the plurality of analog weights. The device also comprises a device controller configured to program the plurality of analog weights to the CIM module based on the digital weight references and determine degradation of one or more analog weights. The digital weight references in the digital weight storage unit are populated with values from a host device. Degraded analog weights in the CIM module are replaced with corresponding digital weight references from the digital weight storage unit without reference to the host device.

Abstract: A built-in self-test (BIST) circuit and a BIST method for Physical Unclonable Function (PUF) quality check are provided. The BIST circuit may include a PUF array, a readout circuit coupled to the PUF array, and a first comparing circuit coupled to the readout circuit. The PUF array may include a plurality of PUF units, wherein each of the PUF units includes a first cell and a second cell. The readout circuit may be configured to output an output bit from the first cell and output a parity bit from the second cell. The first comparing circuit may be configured to compare an output string with a parity string to generate a parity check result, wherein the output string includes output bits respectively read from selected PUF units of the PUF units, and the parity string includes parity bits read from the selected PUF units.

Abstract: The present disclosure is directed to a data storage device that includes a refresh monitor based on a learning based feedback control. The refresh monitor is used to control refresh operations to account for effects of writes to media, e.g., adjacent track interference (ATI). Read operations are analyzed to derive damage information usable to update one or more probability distributions, upon which the learning is updated or reinforced and carried forward. In one embodiments, the data storage device includes control circuitry configured to maintain a refresh monitor based on a learning system, analyze a read operation with the refresh monitor; adjust the refresh monitor by updating the one or more probability distributions based on the analyzed read operation; and execute a refresh operation to refresh data based on the adjusted refresh monitor.

Abstract: Methods, systems, and devices for memory health status reporting are described. A memory device may output to a host device a parameter value, which may be indicative of metric or condition related to the performance or reliability (e.g., a health status) of the memory device of the memory device. The host device may thereby determine that the memory device is degraded, possibly prior to device or system failure. Based on the parameter value, the host device may take preventative action, such as quarantining the memory device, deactivating the memory device, or swapping the memory device for another memory device.

Abstract: Secure distributed storage and transmission of electronic content is provided over at least one communication network. At least one data file is received and parsed into a plurality of segments, wherein each one of the segments has a respective size. Thereafter, each of the plurality of segments is divided into a plurality of slices, wherein each one of the slices has a respective size. A plurality of data chunks are encoded, each data chunk comprising a portion of at least two of the slices, wherein no portion comprises an entire slice. The data chunks are packaged with at least metadata, and each of the packages is assigned to respective remote storage nodes. Each of the packages is transmitted to the respectively assigned remote storage node.

Abstract: A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits; a parity permutator configured to perform parity permutation by interleaving the parity bits and group-wise interleaving a plurality of bit groups including the interleaved parity bits; and a puncturer configured to select some of the parity bits in the group-wise interleaved bit groups, and puncture the selected parity bits, wherein the parity permutator group-wise interleaves the bit groups such that some of the bit groups are positioned at predetermined positions, respectively, and a remainder of the bit groups are positioned without an order within the group-wise interleaved bit groups so that the puncturer selects parity bits included in the some of the bit groups positioned at the predetermined positions sequentially and selects parity bits included in the remainder of the bit groups without an order.

Abstract: Provided in the present disclosure are an electric apparatus and method for a wireless communication network control end, and electronic apparatus and method for a wireless communication network node. The electronic apparatus for the wireless communication network control end includes a processing circuit. The processing circuit is capable of determining how to divide wireless communication transmission resources in a predetermined domain, the divided transmission resources being employed for first-time transmission and re-transmission of a network node, respectively. The processing circuit is also capable of generating configuration information containing information of a dividing manner of the wireless communication transmission resources.

Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.

Abstract: Packet flows between a transmitter and a receiver in an unreliable and unordered switched packet network may be established as a result of receiving a second packet comprising a second memory operation on a memory address. The transmission of memory load command packets followed by memory store command packets in the packet flow may be serialized, and a synchronization operation may be executed between the transmitter and the receiver when a packet count at the receiver satisfies a number of data packets in the packet flow.

Abstract: As system is provided for performing a method of receiving a superposition state defined by a sum of a plurality of addends, wherein each addend of the plurality of addends is a product between a corresponding coefficient of a plurality of coefficients and a corresponding state of a plurality of states encoded with block unary encoding. The system may identify at least one error state, of the plurality of states, having a string value that is not a block unary code string of a set of block unary code strings. The system may compute an updated superposition state based on the plurality of states without the error state.

Abstract: A built-in self-test (BIST) method includes providing expanded test patterns to a logic circuit under test, generating a first signature based on a response of the logic circuit to the expanded test patterns, generating a second signature based on the first signature, wherein the second signature is a compressed version of the first signature, selecting one of the first signature or the second signature in response to a control signal, comparing the selected one of the first signature or the second signature to an expected signature, and, based on the comparison of the selected one of the first signature or the second signature to the expected signature, determining that the logic circuit passes or fails BIST.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.

Abstract: A data storage device is disclosed. The data storage device comprises a controller and a data storage unit. The controller comprises a firmware. The data storage unit comprises a first system storage sector and a second system storage sector. A state of the first system storage sector is preset as a display state by the firmware, and a state of the second system storage sector is preset as a hidden state by the firmware. The first system storage sector stores an original operating system, and the second system storage sector stores a backup operating system. When the original operating system damages, the firmware will recover the original operating system in the first system storage sector via the backup operating system in the second system storage sector; afterwards, a boot operation can be executed via the original operating system recovered, again.

Abstract: A memory sub-system configured to dynamically select an option to process encoded data retrieved from memory cells of a memory component, based on a prediction generated using signal and noise characteristics of memory cells storing the encoded data. For example, the memory component is enclosed in an integrated circuit and has a calibration circuit. The signal and noise characteristics are measured by the calibration circuit as a byproduct of executing a read command in the memory component to retrieve the encoded data. A data integrity classifier configured in the memory sub-system generates a prediction based on the signal and noise characteristics. Based on the prediction, the memory sub-system selects an option from a plurality of options configured in the memory sub-system to process the encoded data.

Abstract: The disclosure provides a method and a device in a User Equipment (UE) and a base station for wireless communication. A first node generates a first bit block, performs channel coding and then transmits a first radio signal. The first bit block comprising all bits in a second bit block and all bits in a third bit block is used for an input of the channel coding, and an output of the channel coding is used for generating the first radio signal. A Cyclic Redundancy Check (CRC) bit block of a fourth bit block is used for generating the third bit block. The fourth bit block comprises all bits in the second bit block and all bits in a fifth bit block, the bits in the fifth bit block are of fixed values, and the fifth bit block is composed of K bits, the K being a positive integer.

Abstract: Systems, apparatus and methods are provided for providing an error correction code (ECC) architecture with flexible memory mapping. An apparatus may include an error correction code (ECC) engine, a multi-channel interface for one or more non-volatile storage devices, a memory including a plurality of memory units, a storage containing a plurality of mapping entries to indicate allocation status of the plurality of memory units and a memory mapping manager. The plurality of memory units may be coupled to the ECC engine and the multi-channel interface. The memory mapping manager may be configured to control allocation of the plurality of memory units and set allocation status in the plurality of mapping entries.

Abstract: A link interface is provided of a communication protocol using idle flow control digits (flits) to maintain link continuity. The link interface includes: a physical layer of the communication protocol configured to transmit and receive flits via a link, wherein the communication protocol provides for idle flits of first and second sizes for maintaining link continuity, the first size being smaller than the second size; and a data link layer configured to transmit and receive flits to/from the physical layer. The data link layer is configured to remove idle flits of the first size received from the physical layer and to report cyclic redundancy check errors of filtered first sized idle flits in a correct order in relation to other flits.

Abstract: Systems, apparatus and methods are provided for providing an error correction code (ECC) architecture with flexible memory mapping. An apparatus may include an error correction code (ECC) engine, a multi-channel interface for one or more non-volatile storage devices, a memory including a plurality of memory units, a storage containing a plurality of mapping entries to indicate allocation status of the plurality of memory units and a memory mapping manager. The plurality of memory units may be coupled to the ECC engine and the multi-channel interface. The memory mapping manager may be configured to control allocation of the plurality of memory units and set allocation status in the plurality of mapping entries.