Abstract: A memory sub-system causing execution of a first wordline leakage test of a first wordline group of a set of wordline groups of a memory block in response to determining a temperature of the memory block is within a threshold temperature range. A first result of the first wordline leakage test is determined. A second wordline leakage test of a second wordline group is caused to be executed and a second result is determined. A determination is made that the first result of the first wordline leakage test of the first wordline group satisfies a first condition. A determination is made that the second result of the second wordline leakage test of the second wordline group satisfies a second condition. In response to satisfaction of the conditions, an action is executed.

Abstract: A technique is provided for constraining access to memory using capabilities. An apparatus is provided that has processing circuitry for performing operations during which access request to memory are generated, wherein the processing circuitry is arranged to generate memory addresses for the access requests using capabilities that provide a pointer value and associated constraining information. The apparatus also provides capability generation circuitry, that is responsive to the processing circuitry executing a capability generating instruction that identifies a location in a literal pool of the memory, to retrieve a literal value from the location in the literal pool, and to produce a generated capability in which the pointer value of the generated capability is determined from the literal value. The constraining information of the generated capability is selected from a limited set of options in dependence on information specified by the capability generating instruction.

Abstract: Commands can be placed in a shadow submission queue (SQ) that is invisible to a host device, and corresponding data can be placed in a temporary buffer. Upon executing any command, the shadow SQ is searched for any commands that can be executed. In so doing, sequential writing to a zone is possible for out of order fetched commands. To further increase granularity, the order can be on a per page basis within a zone such that commands can be taken out of order throughout the zone, but if a page can be filled, even if the page is out of order, the page can be written. In either the zone granularity or the page granularity situation, commands can be placed in the shadow SQ so long as there is sufficient storage available in the temporary buffer for both the data of the command and any gaps.

Abstract: A memory is disclosed. The memory may include a first data structure. The first data structure may include a first field to store a first data relating to a command. The memory may also include a second data structure. The second data structure may include a second field to store a second data relating to the command. A first queue stored in the memory may include the first data structure. A second queue stored in the memory may include the second data structure.

Abstract: According to an embodiment of the present technology, a storage device includes a non-volatile memory device including a first memory block area and a second memory block area, and a storage controller configured to control the non-volatile memory device, determine a target erase count based on a generated assignment request among a first assignment request and a second assignment request, and assign a target memory block corresponding to the target erase count, as a memory block corresponding to the generated assignment request, to a shared block pool. The first assignment request corresponds to a memory block of a first type in the first memory block area, the second assignment request corresponds to a memory block of a second type in the first memory block area, and the target memory block is included in the first memory block area.

Abstract: A memory is disclosed. The memory may include a first data structure. The first data structure may include a first field to store a first data relating to a command. The memory may also include a second data structure. The second data structure may include a second field to store a second data relating to the command. A first queue stored in the memory may include the first data structure. A second queue stored in the memory may include the second data structure.

Abstract: Provided herein is a memory controller for controlling a memory device. The memory controller includes a workload detector configured to determine a change in workload based on reception of a changed request from a host or a change in clock received from an external device, a device performance controller configured to determine, if the workload is determined as changed, read performance based on a ratio of a size of data output to the host to a size of data requested from the host every preset period and configured to output a read-look-ahead (RLA) command to the memory device based on the determined read performance, a buffer memory configured to store data read from the memory device in response to the RLA command and a memory size controller configured to control a size of the buffer memory. The RLA command instructs to output data which is frequently requested from the host.

Abstract: An embodiment of an electronic apparatus may comprise one or more substrates and a controller coupled to the one or more substrates, the controller including circuitry to apply a reliability, availability, and serviceability (RAS) policy for access to a memory in accordance with a first RAS scheme, change the applied RAS policy in accordance with a second RAS scheme at runtime, where the second RAS scheme is different from the first RAS scheme, and access the memory in accordance with the applied RAS policy. Other embodiments are disclosed and claimed.

Abstract: Disclosed herein is a method for memory management in a memory disaggregation environment. The method includes generating virtual memory based on multiple first memory devices, determining whether a condition for allocation acceleration is satisfied by the first memory devices, and allocating a memory page to the first memory devices based on whether the condition for allocation acceleration is satisfied.

Abstract: A memory device configured to perform in-memory processing includes a plurality of in-memory arithmetic units each configured to perform in-memory processing of a pipelined arithmetic operation, and a plurality of memory banks allocated to the in-memory arithmetic units such that a set of n memory banks is allocated to each of the in-memory operation units, each memory bank configured to perform an access operation of data requested from the in-memory arithmetic units while the pipelined arithmetic operation is performed. Each of the in-memory arithmetic units is configured to operate at a first operating frequency that is less than or equal to a product of n and a second operating frequency of each of the memory banks.

Abstract: The present disclosure relates to a computer implemented method for verification of a cache memory of a device under test. The method comprises executing a cache verification process configured for accessing via an interface and verifying the cache memory of the device under test. Cache accesses to the cache memory of the device under test by the cache verification process via the interface are monitored. A cache access by the cache verification process via the interface is detected. In response to the detecting of the cache access a target of the detected cache access is determined and the cache memory is modified for providing a pre-defined cache read-out result for the detected cache access. Via the interface the pre-defined cache read-out result is returned to the cache verification process in response to the detected cache access.

Abstract: The present disclosure includes systems, apparatuses, and methods related to memory channel controller operation. For example, a data type associated with an access request may be determined. The access request may be executed by utilizing, responsive to determining the access request is associated with a first data type, a first memory channel controller coupled to a first memory device to access a first memory address range, associated with the first data type, allocated to the first memory device. The access request may be executed by utilizing, responsive to determining the access request is associated with a second data type, the first memory channel controller and a second memory channel controller coupled to a second memory device to access a second memory address range, associated with the second data type, allocated among the first memory device and the second memory device.

Abstract: Methods, systems, and devices for array access with receiver masking are described. A first device may issue to a second device a first sequence of write commands for a set of data. The first sequence of write commands may indicate different memory addresses in an order. After issuing the first sequence of write commands, the first device may issue to the second device a second sequence of read commands for the set of data. The second sequence of read commands may indicate the different memory addresses in the same order as the first sequence of write commands Based on issuing the second sequence of read commands, the first device may receive the set of data from the second device.

Abstract: A method is provided that includes searching tags in a tag group comprised in a tagged memory system for an available tag line during a clock cycle, wherein the tagged memory system includes a plurality of tag lines having respective tags and wherein the tags are divided into a plurality of non-overlapping tag groups, and searching tags in a next tag group of the plurality of tag groups for an available tag line during a next clock cycle when the searching in the tag group does not find an available tag line.

Abstract: Disclosed are techniques for memory resource control using Memory System Resource Partitioning and Monitoring (MPAM). In an aspect, a method of memory-system resource usage monitoring on a processing unit may include attaching a partition identifier from a set of partition identifiers to each memory access request of a plurality of memory access requests on an interconnect. The method may also include interleaving each memory access request of the plurality of memory access requests to a set of memory system components. The method may also include determining a first bandwidth associated with a first memory system component of the set of memory system components. The method may also include applying the first bandwidth associated with the first memory system component to one or more other memory system components of the set of memory system components based at least in part on the interleaving each memory access request.

Abstract: A method for sizing backup infrastructure. The method includes: receiving a sizing request including an asset protection policy covering an asset of the backup infrastructure, the asset protection policy at least specifying the asset; based on receiving the sizing request: creating an asset snapshot of the asset; mounting the asset snapshot to obtain a mounted asset snapshot through which asset snapshot data of the asset snapshot is accessible; partitioning the asset snapshot data into a plurality of asset snapshot data slices; computing, at least based on a cardinality of the plurality of asset snapshot data slices, a number of proxy nodes of the backup infrastructure required to collectively perform a prospective backup operation entailing the asset snapshot data; and providing, in reply to the sizing request, a sizing response at least specifying the number of proxy nodes required to collectively perform the prospective backup operation.

Abstract: A method for optimizing data storage includes obtaining a data object for storage at memory hardware in communication with data processing hardware. The memory hardware includes a plurality of storage devices, each storage device of the plurality of storage devices including storage parameters different from each other storage device of the plurality of storage devices. The method also includes determining one or more data object parameters associated with the data object and predicting, using a model and the data object parameters and the storage parameters, an object temperature representative of a frequency of access for the data object and an object lifetime representative of an amount of time the data object is to be stored. The method further includes selecting, using the predicted object temperature and object lifetime, one of the storage devices, and storing the data object at the selected one of the storage devices.

Abstract: In accordance with an embodiment, a system on chip includes: a plurality of master equipment; a plurality of slave resources, where a slave resource of the plurality of slave resources comprises a memory device includes a first memory area; an interconnection circuit; and a check circuit. A first master equipment is configured to define initial access rights for the first memory area, and to delegate access management of the first memory area to a second master equipment. The second master equipment is configured to define for the first memory area, particular access rights from the initial access rights associated with the first memory area and access right rules; and the check circuit is configured to check whether a transaction intended for the first memory area is indeed authorized to access the first memory area using applicable access rights associated with the first memory area.

Abstract: Described are techniques for creating a point-in-time backup of application data stored on disparate storage systems. The techniques include initiating a snapshot of the first datastore. The techniques further include initiating a suspension of delete operations at the second datastore to preserve immutable application data stored on the second datastore. The techniques further include initiating a background copy of the second datastore. The techniques further include initiating a resumption of the delete operations at the second datastore in response to completion of the background copy of the second datastore.

Abstract: A memory controller circuit includes a first channel circuit having a first programmable switch circuit that is programmable to provide a first request signal indicating a first data access request to a memory circuit. The first programmable switch circuit is programmable to provide a first write data signal indicating first data for storage in the memory circuit. The memory controller circuit includes a second channel circuit having a second programmable switch circuit that is programmable to provide one of the first request signal received from the first programmable switch circuit or a second request signal indicating a second data access request to the memory circuit. The second programmable switch circuit is programmable to provide one of the first write data signal received from the first programmable switch circuit or a second write data signal indicating second data for storage in the memory circuit.