Abstract: An apparatus comprises memory storage circuitry comprising a plurality of memory storage locations to store data; an interface to receive an address from a requester; decryption circuitry to obtain a decrypted address by decrypting, based on a decryption key, an address received from the requester; and access control circuitry to select, based on the decrypted address obtained by the decryption circuitry, a memory storage location of the memory storage circuitry to be accessed.

Abstract: A system includes a first memory component of a first memory type, a second memory component of a second memory type with a higher access latency than the first memory component, and a third memory component of a third memory type with a higher access latency than the first and second memory components. The system further includes a processing device to identify a section of a data page stored in the first memory component, and access patterns associated with the data page and the section of the data page. The processing device determines to cache the data page at the second memory component based on the access patterns, copying the section of the data page stored in the first memory component to the second memory component. The processing device then copies additional sections of the data page stored at the third memory component to the second memory component.

Abstract: A data storage device may include a nonvolatile memory device including a plurality of memory blocks and a controller configured to perform a block scan operation for checking valid page counts of closed blocks, when the number of free blocks among the plurality of memory blocks is equal to or less than a threshold number, select a victim block from the closed blocks among the plurality of memory blocks, and perform a garbage collection operation on the victim block. The controller may change an index of a scan start block among the closed blocks whenever performing the block scan operation.

Abstract: An embodiment of a memory device includes technology for a memory cell array logically organized in two or more banks of at least two rows and two columns per bank, and two or more local caches respectively coupled to the two or more banks of the memory cell array, where each local cache has a size which is an integer multiple of a memory page size of the memory cell array. Other embodiments are disclosed and claimed.

Abstract: A method is provided that includes searching tags in a tag group comprised in a tagged memory system for an available tag line during a clock cycle, wherein the tagged memory system includes a plurality of tag lines having respective tags and wherein the tags are divided into a plurality of non-overlapping tag groups, and searching tags in a next tag group of the plurality of tag groups for an available tag line during a next clock cycle when the searching in the tag group does not find an available tag line.

Abstract: Embodiments include methods, apparatus, or processors configured to access a tracking enabled storage volume associated with a container; perform a full backup of the storage volume, where performing the full backup includes defining a full backup point; perform a first incremental backup of the storage volume based on the full backup point, where performing the first incremental backup includes defining a current backup point; determine whether a backup termination condition has been met; upon determining that the backup termination condition has not been met: performing a subsequent incremental backup of the storage volume based on the current backup point; and updating the current backup point. Embodiments may restore the tracking enabled storage volume from the full backup and the incremental backups.

Abstract: An aspect includes providing a scratchpad memory to at least one persistent storage device of a plurality of persistent storage devices in a storage array. The scratchpad memory includes non-volatile storage. An aspect also includes designating the scratchpad memory for storing data corresponding to write operations implemented by a storage system, apportioning the scratchpad memory among each storage controller of a plurality of storage controllers in the storage system, and receiving, at the scratchpad memory, a write request from one of the storage controllers. An aspect further includes writing data of the write request to a location in the scratchpad memory based on the apportioning and corresponding to the one of the storage controllers.

Abstract: A cache system, having: a first cache set; a second cache set; and a logic circuit coupled to a processor to control the caches based on at least respective first and second registers. When a connection to an address bus receives a memory address from the processor, the logic circuit is configured to: generate a set index from at least the address; and determine whether the generated set index matches with a content stored in the first register or with a content stored in the second register. And, the logic circuit is configured to implement a command via the first cache set in response to the generated set index matching with the content stored in the first register and via the second cache set in response to the generated set index matching with the content stored in the second register.

Abstract: A memory system includes a memory device including a first memory block and a second memory block; and a controller suitable for controlling the memory device, wherein the controller includes a sequential index calculator suitable for calculating a sequential index based on first logical block address (LBA) information and second LBA information that are written in the first memory block; an internal operation determining component suitable for determining whether an internal operation is to be performed on the first memory block, by comparing the sequential index of the first memory block with a threshold value; and an internal operation performing component suitable for migrating pieces of LBA information stored in the first memory block to the second memory block to rearrange the pieces of LBA information, when it is determined that the internal operation is to be performed on the first memory block.

Abstract: Aspects of a storage device include a memory comprising a plurality of memory locations each associated with a physical address, the memory configured to store a plurality of video frames received from a host device at the physical addresses, each of the video frames being associated with a logical address; and a controller configured to store in a partition of the memory the logical addresses for a subset of the video frames, the controller being configured to provide the host access to the partition to read the logical addresses during rapid playback of the video frames. Aspects of the host device include a processor configured to write the video frames to the storage device, to identify the subset of the video frames to the storage device, and during rapid playback, to access the storage device to read the logical address for each video frame in the subset.

Abstract: Provides an efficient method for aligned heap allocations based upon spare space management, provides an efficient method for MPU region allocations based upon aligned subregion allocations, and provides integrated block pools for small data blocks with heap backup if size or alignment requirements cannot be met from pools or pools are empty. The operation of malloc( ), calloc( ), realloc( ) and free( ) on pool blocks versus heap blocks is transparent to application code. These methods are suitable for limited-memory, real-time systems as well as for general-purpose systems.

Abstract: Embodiments herein describe a reconfigurable integrated circuit (IC) where data can be retained in memory when performing a partial reconfiguration. Partial reconfiguration includes reconfiguring programmable logic in the IC while certain functions of the IC remain operational or active. In one embodiment, the reconfigurable IC includes control logic for saving or retaining data in the IC during a partial reconfiguration. That is, rather than clearing the memory elements, the user can specify that the memory blocks containing certain data should be retained while the other memory blocks can be cleared. In this manner, the data can be retained in the IC during a partial reconfiguration which saves time, power, and cost. Once partial reconfiguration is complete, the newly configured programmable logic can retrieve and process the saved data from the on-chip memory.

Abstract: A method for performing acceleration of simultaneous access to shared data may include providing a plurality of groups of cores and a plurality of shared memory structures, providing a pod comprising the plurality of groups of cores linked by a common broadcast channel, and coordinating each shared memory structure to provide a logically unified memory structure. Each memory structure may be associated with a group of cores, and each group of cores may include one or more cores. The common broadcast channel may be operatively coupled to each shared memory structure. The coordinating each shared memory structure may include identifying a simultaneous read-reuse load to a first shared memory structure, fetching data corresponding to the simultaneous read-reuse load, and forwarding the data to shared memory structures other than the first shared memory structure and to groups of cores other than a first group of cores via the broadcast channel.

Abstract: To create a backup of a live (running) virtual machine, a backup agent may take a snapshot of the virtual machine, backup the virtual machine from the snapshot disk, and delete the snapshot. Deleting the snapshot initiates a snapshot consolidation process where delta disks of the virtual machine are collapsed. A virtual disk layer sets up a mirror driver between a current virtual disk and a target virtual disk. Data sectors of the delta disk are copied over to the target virtual disk in a single pass, while the mirror driver mirrors write request for the current virtual disk to the target virtual disk.

Abstract: An address translation facility is provided for multiple virtualization levels, where a guest virtual address may be translated to a guest non-virtual address, the guest non-virtual address corresponding without translation to a host virtual address, and the host virtual address may be translated to a host non-virtual address, where translation within a virtualization level may be specified as a sequence of accesses to address translation tables. The address translation facility may include a first translation engine and a second translation engine, where the first and second translation engines each have capacity to perform address translation within a single virtualization level of the multiple virtualization levels.

Abstract: An apparatus includes at least one processing device comprising a processor coupled to a memory, with the processing device being configured to identify a first storage volume of a first snapshot group of a storage system, to identify a second storage volume that is not part of the first snapshot group of the storage system but contains at least a threshold amount of matching data relative to the first storage volume, and to merge the second storage volume into the first snapshot group. The processing device illustratively comprises a storage controller of the storage system. The storage system may be implemented as a clustered storage system comprising a plurality of storage nodes. Each storage node may comprise a set of processing modules of a distributed storage controller of the clustered storage system.

Abstract: Embodiments of the present invention allow for fast cache reheat by periodically storing a snapshot of information identifying the contents of the cache at the time of the snapshot, and then using the information from the last snapshot to restore the contents of the cache following an event that causes loss or corruption of cache contents such as a loss of power or system reset. Since there can be a time gap between the taking of a snapshot and such an event, the actual contents of the cache, and hence the corresponding data stored in a data store, may have changed since the last snapshot was taken. Thus, the information stored at the last snapshot is used to retrieve current data from the data store for use in restoring the contents of the cache.

Abstract: The present invention provides a system on chip (SoC), wherein the SoC comprises a first processor, a second processor and a memory. The memory stores a first parameter and a second parameter, wherein the first parameter is set by the first processor to indicate whether a specific region of the memory is locked or unlocked, and the second parameter is set by the first processor to indicate whether the specific region of the memory is locked or unlocked. In the operations of the SoC, before the first processor intends or prepares to access the specific region, the first processor refers to the second parameter to determine if the specific region is allowed to be accessed by the first processor.

Abstract: A method for writing a plurality of byte arrays to a file arranged in one or more existing data pages, comprising the steps of: identifying a data page corresponding to a first offset; reserving an array of reserved bytes at the first offset, identifying a data page corresponding to the second offset; writing the second byte array at the second offset; writing the first byte array in the array of reserved bytes; determining whether the data pages corresponding to the first offset is ready for uploading to a remote memory source; and uploading the data pages corresponding to the first offset to the remote memory source.

Abstract: This disclosure relates to optimizing write requests based on an object dependency graph. An example method generally includes receiving, from a client device, a write request specifying an object to be written to the data store. A gateway server determines, based on an object dependency graph associated with the specified object and identifying relationships between the specified object and one or more dependency objects, one or more dependency objects to be written to the data store. The gateway server generates a plurality of write requests for the specified object and the one or more dependency objects and generates an execution plan for the plurality of write requests based on the object dependency graph. The gateway server executes the plurality of write requests based on the execution plan.