Patents Examined by Aaron Dehne
  • Method of fabricating antireflective grating pattern and method of fabricating optical device integrated with antireflective grating pattern
    Patent number: 8647903
    Abstract: A method of fabricating an antireflective grating pattern and a method of fabricating an optical device integrated with an antireflective grating pattern are provided. The method of fabricating the antireflective grating pattern includes forming a photoresist (PR) pattern on a substrate using a hologram lithography process, forming a PR lens pattern having a predetermined radius of curvature by reflowing the PR pattern, and etching the entire surface of the substrate including the PR lens pattern to form a wedge-type or parabola-type antireflective subwavelength grating (SWG) pattern having a pointed tip on a top surface of the substrate. In this method, a fabrication process is simplified, the reflection of light caused by a difference in refractive index between the air and a semiconductor material can be minimized, and the antireflective grating pattern can be easily applied to optical devices.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: February 11, 2014
    Assignee: Gwangju Institute of Science and Technology
    Inventors: Yong Tak Lee, Young Min Song
  • Semiconductor light-emitting device
    Patent number: 8648377
    Abstract: A semiconductor light-emitting device including a substrate, an n-type semiconductor layer formed on the substrate, an active layer laminated on the n-type semiconductor layer and capable of emitting a light, a p-type semiconductor layer laminated on the active layer, an n-electrode which is disposed on a lower surface of the semiconductor substrate or on the n-type semiconductor layer and spaced away from the active layer and p-type semiconductor layer, and a p-electrode which is disposed on the p-type semiconductor layer and includes a reflective ohmic metal layer formed on the dot-like metallic layer, wherein the light emitted from the active layer is extracted externally from the substrate side.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: February 11, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eiji Muramoto, Shinya Nunoue
  • Light emitting diode
    Patent number: 8633042
    Abstract: A light emitting diode includes a substrate, a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode, a transparent conductive layer, a second electrode and a metal grating. The first semiconductor layer, the active layer, and the second semiconductor layer are orderly stacked on the substrate. The first electrode is electrically connected to the first semiconductor layer. The transparent conductive layer is located on a surface of the second semiconductor layer away from the substrate. The second electrode is electrically connected to the transparent conductive layer. The metal grating is located on a surface of the transparent conductive layer away from the substrate. The metal grating is a two-dimensional array of a plurality of metal micro-structures.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: January 21, 2014
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Jun Zhu, Peng Ji, Feng-Lei Yang, Guo-Fan Jin
  • Capacitors in integrated circuits and methods of fabrication thereof
    Patent number: 8618635
    Abstract: In one embodiment, a capacitor includes a first via level having first metal bars and first vias, such that the first metal bars are coupled to a first potential node. The first metal bars are longer than the first vias. Second metal bars and second vias are disposed in a second via level, the second metal bars are coupled to the first potential node. The second metal bars are longer than the second vias. The second via level is above the first via level and the first metal bars are parallel to the second metal bars. Each of the first metal bars has a first end, an opposite second end, and a middle portion between the first and the second ends. Each of the middle portions of the first metal bars and the second ends of the first metal bars do not contact any metal line.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: December 31, 2013
    Assignee: Infineon Technologies AG
    Inventors: Sunoo Kim, Moosung Chae, Bum Ki Moon
  • Semiconductor device and manufacturing method of the same
    Patent number: 8614469
    Abstract: A semiconductor device capable of improving the driving power and a manufacturing method therefor are provided. In a semiconductor device, a gate structure formed by successively stacking a gate oxide film and a silicon layer is arranged over a semiconductor substrate. An oxide film is arranged long the lateral side of the gate structure and another oxide film is arranged along the lateral side of the oxide film and the upper surface of the substrate. In the side wall oxide film comprising these oxide films, the minimum value of the thickness of the first layer along the lateral side of the gate structure is less than the thickness of the second layer along the upper surface of the substrate.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: December 24, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Toshifumi Iwasaki, Yoshihiko Kusakabe
  • Wind turbine rotor blade and pitch regulated wind turbine
    Patent number: 8602739
    Abstract: A wind turbine rotor blade with an airfoil profile having an upwind side, a downwind side is provided. A stall inducing device is located at the upwind side of the airfoil profile.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: December 10, 2013
    Assignee: Siemens Aktiengesellschaft
    Inventors: Peder Bay Enevoldsen, Søren Hjort, Jesper Laursen, Anders Vangsgaard Nielsen, Rune Rubak
  • White light emitting device, backlight, liquid crystal display device, and illuminating device
    Patent number: 8598618
    Abstract: A white light emitting device includes a blue light emitting diode chip that emits blue light in a specific wavelength band, a first resin layer that seals the blue light emitting diode chip and includes a cured product of silicone resin, and a second resin layer that covers the first resin layer and includes phosphor powder, which absorbs the blue light and emits light in a specific wavelength band, and a cured product of transparent resin. The phosphor powder has a composition represented by the following Formula (1): (Sr1-x-yBaxEuy)2SiO4??(1) (in Formula (1), x and y satisfy a condition that 0.05<x<0.5 and 0.05<y<0.3.) The first resin layer has thickness within a range of 200 ?m to 2000 ?m. The white light emitting device has high luminance for a long period.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: December 3, 2013
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Materials Co., Ltd.
    Inventors: Tsutomu Ishii, Hajime Takeuchi, Ryo Sakai, Yasumasa Ooya, Yasuhiro Shirakawa
  • Compound semiconductor device and method of manufacturing the same
    Patent number: 8581300
    Abstract: An embodiment of a compound semiconductor device includes: a substrate; an electron channel layer and an electron supply layer formed over the substrate; a gate electrode, a source electrode and a drain electrode formed on or above the electron supply layer; and a p-type semiconductor layer formed between the electron supply layer and the gate electrode. The p-type semiconductor layer contains, as a p-type impurity, an element same as that being contained in at least either of the electron channel layer and the electron supply layer.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: November 12, 2013
    Assignee: Fujitsu Limited
    Inventor: Atsushi Yamada
  • Semiconductor device
    Patent number: 8569843
    Abstract: A bidirectional switch includes a plurality of unit cells 11 including a first ohmic electrode 15, a first gate electrode 17, a second gate electrode 18, and a second ohmic electrode 16. The first gate electrodes 15 are electrically connected via a first interconnection 31 to a first gate electrode pad 43. The second gate electrodes 18 are electrically connected via a second interconnection 32 to a second gate electrode pad 44. A unit cell 11 including a first gate electrode 17 having the shortest interconnect distance from the first gate electrode pad 43 includes a second gate electrode 18 having the shortest interconnect distance from the second gate electrode pad 44.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: October 29, 2013
    Assignee: Panasonic Corporation
    Inventors: Manabu Yanagihara, Kazushi Nakazawa, Tatsuo Morita, Yasuhiro Uemoto
  • Post passivation interconnect with oxidation prevention layer
    Patent number: 8569887
    Abstract: A copper interconnect line formed on a passivation layer is protected by a copper-containing material layer including a group III element, a group IV element, a group V element or combinations thereof.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: October 29, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Yi-Wen Wu, Chung-Shi Liu
  • Mitigation of plating stub resonance by controlling surface roughness
    Patent number: 8569873
    Abstract: Plating stub resonance in a circuit board may be mitigated by increasing surface roughness of the plating stub conductor. Roughening the plating stub increases its resistance due to the skin effect at higher frequencies, which decreases the quality factor of the transmission line and consequently increases the damping factor, to reduce any resonance that would occur in the plating stub as formed prior to roughening. The surface roughness can be increased in a variety of ways, including chemical processes, by selectively applying a laser beam, or by applying an etch-resistance material in selected locations.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: October 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Bhyrav M. Mutnury, Moises Cases, Tae Hong Kim, Nanju Na
  • Semiconductor device having a blocking structure and method of manufacturing the same
    Patent number: 8564072
    Abstract: A semiconductor device includes a blocking structure between a metal layer and at least one underlying layer. The blocking structure has a first layer configured for preventing diffusion of metal from the metal layer into the at least one underlying layer, and a second layer configured for enhancing electrical performance of the semiconductor device.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: October 22, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bor-Wen Chan, Hsueh Wen Tsau
  • Semiconductor device
    Patent number: 8552553
    Abstract: The present invention relates to a semiconductor device. The semiconductor device includes a substrate and a chip. The chip is electrically connected to the substrate. The chip includes a chip body, at least one chip pad, a first passivation, an under ball metal layer and at least one metal pillar structure. The chip pad is disposed adjacent to an active surface of the chip body. The first passivation is disposed adjacent to the active surface, and exposes part of the chip pad. The under ball metal layer is disposed adjacent to the chip pad. The metal pillar structure contacts the under ball metal layer to form a first contact surface having a first diameter. The metal pillar structure is electrically connected to a substrate pad of the substrate to form a second contact surface having a second diameter. The ratio of the first diameter to the second diameter is between 0.7 and 1.0.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: October 8, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Jian-Wen Lo, Chien-Fan Chen
  • Embedded semiconductive chips in reconstituted wafers, and systems containing same
    Patent number: 8535989
    Abstract: A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: September 17, 2013
    Assignee: Intel Corporation
    Inventors: Robert L. Sankman, John S. Guzek
  • Roll-to-roll non-vacuum deposition of transparent conductive electrodes
    Patent number: 8530262
    Abstract: Methods and devices are provided for improved photovoltaic devices. Non-vacuum deposition of transparent conductive electrodes in a roll-to-roll manufacturing environment is disclosed. In one embodiment, a method is provided for forming a photovoltaic device. The method comprises processing a precursor layer in one or more steps to form a photovoltaic absorber layer; depositing a smoothing layer to fill gaps and depression in the absorber layer to reduce a roughness of the absorber layer; adding an insulating layer over the smooth layer; and forming a web-like layer of conductive material over the insulating layer. By way of nonlimiting example, the web-like layer of conductive material comprises a plurality of carbon nanotubes. In some embodiments, the absorber layer is a group IB-IIIA-VIA absorber layer.
    Type: Grant
    Filed: March 2, 2009
    Date of Patent: September 10, 2013
    Assignee: Nanosolar, Inc.
    Inventors: Jeroen K. J. Van Duren, Matthew R. Robinson, James R. Sheats
  • Angled implantation for deep submicron device optimization
    Patent number: 8519403
    Abstract: A method for forming a submicron device includes depositing a hard mask over a first region that includes a polysilicon well of a first dopant type and a gate of a second dopant type and a second region that includes a polysilicon well of a second dopant type and a gate of a first dopant type. The hard mask over the first region is removed. Angled implantation of the first dopant type is performed to form pockets under the gate of the second dopant type.
    Type: Grant
    Filed: February 4, 2011
    Date of Patent: August 27, 2013
    Assignee: Altera Corporation
    Inventors: Che Ta Hsu, Christopher J. Pass, Dale Ibbotson, Jeffrey T. Watt, Yanzhong Xu
  • High voltage devices, systems, and methods for forming the high voltage devices
    Patent number: 8507988
    Abstract: A high voltage (HV) device includes a gate dielectric structure over a substrate. The gate dielectric structure has a first portion and a second portion. The first portion has a first thickness and is over a first well region of a first dopant type in the substrate. The second portion has a second thickness and is over a second well region of a second dopant type. The first thickness is larger than the second thickness. A gate electrode is disposed over the gate dielectric structure. A metallic layer is over and coupled with the gate electrode. The metallic layer extends along a direction of a channel under the gate dielectric structure. At least one source/drain (S/D) region is disposed within the first well region of the first dopant type.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: August 13, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wen Yao, Robert S. J. Pan, Ruey-Hsin Liu, Hsueh-Liang Chou, Puo-Yu Chiang, Chi-Chih Chen, Hsiao Chin Tuan
  • Low triggering voltage DIAC structure
    Patent number: 8497526
    Abstract: In a DIAC-like device that includes an n+ and a p+ region connected to the high voltage node, and an n+ and a p+ region connected to the low voltage node, at least two MOS devices are formed between the n+ and p+ region connected to the high voltage node, and the n+ and p+ region connected to the low voltage node.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: July 30, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Antonio Gallerano, Peter J. Hopper
  • Interface structure for channel mobility improvement in high-k metal gate stack
    Patent number: 8492852
    Abstract: A gate stack structure for field effect transistor (FET) devices includes a nitrogen rich first dielectric layer formed over a semiconductor substrate surface; a nitrogen deficient, oxygen rich second dielectric layer formed on the nitrogen rich first dielectric layer, the first and second dielectric layers forming, in combination, a bi-layer interfacial layer; a high-k dielectric layer formed over the bi-layer interfacial layer; a metal gate conductor layer formed over the high-k dielectric layer; and a work function adjusting dopant species diffused within the high-k dielectric layer and within the nitrogen deficient, oxygen rich second dielectric layer, and wherein the nitrogen rich first dielectric layer serves to separate the work function adjusting dopant species from the semiconductor substrate surface.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Tze-Chiang Chen, Dechao Guo, Philip J. Oldiges, Yanfeng Wang
  • Semiconductor device
    Patent number: 8476677
    Abstract: An aspect of the present invention inheres in a semiconductor device includes a semiconductor region, a source electrode and a drain electrode, which are provided on a main surface of the semiconductor region, a gate electrode exhibiting normally-off characteristics, the gate electrode being provided above the main surface of the semiconductor region while interposing a p-type material film therebetween, and being arranged between the source electrode and the drain electrode, and a fourth electrode that is provided on the main surface of the semiconductor region, and is arranged between the gate electrode and the drain electrode.
    Type: Grant
    Filed: May 8, 2012
    Date of Patent: July 2, 2013
    Assignee: Sanken Electric Co., Ltd.
    Inventors: Osamu Machida, Akio Iwabuchi