Abstract: Semiconductor workpiece carriers and methods for processing semiconductor workpieces are disclosed herein. In one embodiment, a semiconductor workpiece carrier assembly includes (a) a support structure having an opening sized to receive at least a portion of a semiconductor workpiece, and (b) a replaceable carrier positioned at the opening. The replaceable carrier includes a base and an adhesive layer on the base. The base has a surface, and the adhesive layer covers only a section of the surface of the base. The adhesive layer releasably attaches the replaceable carrier to the support structure.

Abstract: A method for forming an STI structure is provided. In one embodiment, a trench is formed in a substrate, the trench having a first sidewall and a second sidewall opposite the first sidewall, the sidewalls extending down to a bottom portion of the trench. An insulating material is deposited to line the surfaces of the sidewalls and the bottom portion. The insulating material proximate the top portions and the bottom portion of the trench are thereafter etched back. The insulating material is deposited to line the inside surfaces of the trench at a rate sufficient to allow a first protruding insulating material deposited on the first sidewall and a second protruding insulating material deposited on the second sidewall to approach theretogether. The steps of etching back and depositing are repeated to have the first and second protruding materials abut, thereby forming a void near the bottom of the trench.

Abstract: An embodiment of a process for manufacturing a power semiconductor device envisages the steps of: providing a body of semiconductor material having a top surface and having a first conductivity; forming columnar regions having a second type of conductivity within the body of semiconductor material, and surface extensions of the columnar regions above the top surface; and forming doped regions having the second type of conductivity, in the proximity of the top surface and in contact with the columnar regions. The doped regions are formed at least partially within the surface extensions of the columnar regions; the surface extensions and the doped regions have a non-planar surface pattern, in particular with a substantially V-shaped groove.

Abstract: Methods of forming nonvolatile memory devices include forming a vertical stack of nonvolatile memory cells on a substrate. This is done by forming a vertical stack of spaced-apart gate electrodes on a first sidewall of a vertical silicon active layer and treating a second sidewall of the vertical silicon active layer in order to reduce crystalline defects within the active layer and/or reduce interface trap densities therein. This treating can include exposing the second sidewall with an oxidizing species that converts a surface of the second sidewall into a silicon dioxide passivation layer. A buried insulating pattern may also be formed directly on the silicon dioxide passivation layer.

Abstract: The present invention provides a multilayer wiring capable of reducing the area of the wiring layer while preventing the property deterioration due to the parasitic capacitance, a semiconductor device, a substrate for display device, and a display device. The multilayer wiring of the present invention includes: a first conductor; a second conductor; and a third conductor. The first conductor is positioned in a (n+1)th conductive layer. The second conductor is positioned in a (n+2)th conductive layer, is electrically connected to a conductor in a layer below the (n+1)th conductive layer through at least a first connection hole in a (n+1)th insulating layer directly below the (n+2)th conductive layer, and is positioned so as not to overlap with the first conductor in a plan view of the main face of the substrate.

Abstract: A carrier for holding a plurality of chip packages and a carrier assembly are provided, wherein the chip package has a central area without solder balls and a peripheral area with solder balls formed thereon. The carrier includes a tray component and a plurality of supports disposed on the tray component, wherein each support holds the central area of a respective chip package. The carrier assembly is formed by stacking a plurality of the carriers through a plurality of peripheral projections disposed at a periphery of each tray component, wherein each peripheral projection has a pin formed thereon and a hole formed thereunder.

Abstract: A rotor assembly for a wind turbine including at least one blade adapted to automatically adjust its shape as a function of rotational speed to create an efficient fluid dynamic profile over a wide range of wind conditions and rotational speeds. The rotor assembly includes at least one blade configured to respond to rotation induced forces to automatically bend in a manner to optimize its wind profile.

Abstract: A semiconductor device includes a semiconductor die and a plurality of lead-free solder bumps disposed on a surface of the semiconductor die. A substrate includes a plurality of metal layers and a plurality of dielectric layers. One of the metal layers includes a plurality of contact pads corresponding to the plurality of lead-free solder bumps, and one of the dielectric layers is an exterior dielectric layer having a plurality of respective openings for the contact pad. A plurality of respective copper posts is disposed on the contact pads. The respective copper post for each contact pad extends from the contact pad through the respective opening for the contact pad. The semiconductor die is mounted on the substrate with connections between the plurality of lead-free solder bumps and the plurality of copper posts.

Abstract: An apparatus includes a process chamber configured to perform an ion implantation process. A cooling platen or electrostatic chuck is provided within the process chamber. The cooling platen or electrostatic chuck is configured to support a semiconductor wafer. The cooling platen or electrostatic chuck has a plurality of temperature zones. Each temperature zone includes at least one fluid conduit within or adjacent to the cooling platen or electrostatic chuck. At least two coolant sources are provided, each fluidly coupled to a respective one of the fluid conduits and configured to supply a respectively different coolant to a respective one of the plurality of temperature zones during the ion implantation process. The coolant sources include respectively different chilling or refrigeration units.

Abstract: A semiconductor light-emitting device including a substrate, an n-type semiconductor layer formed on the substrate, an active layer laminated on the n-type semiconductor layer and capable of emitting a light, a p-type semiconductor layer laminated on the active layer, an n-electrode which is disposed on a lower surface of the semiconductor substrate or on the n-type semiconductor layer and spaced away from the active layer and p-type semiconductor layer, and a p-electrode which is disposed on the p-type semiconductor layer and includes a reflective ohmic metal layer formed on the dot-like metallic layer, wherein the light emitted from the active layer is extracted externally from the substrate side.

Abstract: A fabricating method of an image sensor includes the steps of: providing a substrate; forming sensing elements on the substrate; forming microlenses on the sensing elements; filling a stuffed material on the microlenses, and air regions are formed in the stuffed material; and forming optical filters on the stuffed material.

Abstract: A transducer array on a common substrate includes a membrane and first and second transducer devices. The membrane is formed on the common substrate, and includes a lower layer and an upper layer. The first transducer device includes a first resonator stack formed on at least the lower layer in a first portion of the membrane, the upper layer having a first thickness in the first portion of the membrane. The second transducer device includes a second resonator stack formed on at least the lower layer in a second portion of the membrane, the upper layer having a second thickness in the second portion of the membrane, where the second thickness is different from the first thickness, such that a first resonant frequency of the first transducer device is different from a second resonant frequency of the second transducer device.

Abstract: A method for producing a backside contact of a single p-n junction photovoltaic solar cell is provided. The method includes the steps of: providing a p-type substrate having a back surface; providing a plurality of p+ diffusion regions at the back surface of the substrate; providing a plurality of n+ diffusion regions at the back surface of the substrate in an alternate pattern with the p+ diffusion regions; providing an oxide layer over the p+ and n+ regions; providing an insulating layer over the back surface of the substrate; providing at least one first metal contact at the back surface for the p+ diffusion regions; and providing at least one second metal contact at the back surface for the n+ diffusion regions.

Abstract: A bidirectional switch includes a plurality of unit cells 11 including a first ohmic electrode 15, a first gate electrode 17, a second gate electrode 18, and a second ohmic electrode 16. The first gate electrodes 15 are electrically connected via a first interconnection 31 to a first gate electrode pad 43. The second gate electrodes 18 are electrically connected via a second interconnection 32 to a second gate electrode pad 44. A unit cell 11 including a first gate electrode 17 having the shortest interconnect distance from the first gate electrode pad 43 includes a second gate electrode 18 having the shortest interconnect distance from the second gate electrode pad 44.

Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming a first isolation region in the semiconductor substrate; after the step of forming the first isolation region, forming a metal-oxide-semiconductor (MOS) device at a surface of the semiconductor substrate, wherein the step of forming the MOS device comprises forming a source/drain region; and after the step of forming the MOS device, forming a second isolation region in the semiconductor substrate.

Abstract: Techniques are disclosed for fabricating FinFET transistors (e.g., double-gate, trigate, etc). A sacrificial gate material (such as polysilicon or other suitable material) is deposited on fin structure, and polished to remove topography in the sacrificial gate material layer prior to gate patterning. A flat, topography-free surface (e.g., flatness of 50 nm or better, depending on size of minimum feature being formed) enables subsequent gate patterning and sacrificial gate material opening (via polishing) in a FinFET process flow. Use of the techniques described herein may manifest in structural ways. For instance, a top gate surface is relatively flat (e.g., flatness of 5 to 50 nm, depending on minimum gate height or other minimum feature size) as the gate travels over the fin. Also, a top down inspection of gate lines will generally show no or minimal line edge deviation or perturbation as the line runs over a fin.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a first operational device having a first transistor of a first composition; a second operational device having a second transistor of the first composition; and an isolation transistor disposed between the first and second transistors, the isolation transistor having a second composition different from the first composition.

Abstract: The invention relates to a power semiconductor module including a power semiconductor chip arranged on a substrate and comprising a bottom side facing the substrate, a top side facing away from the substrate, and an electrical contact face arranged on the top side. A bond wire is bonded to the contact face. At least when the power semiconductor module is fastened to a heatsink, a contact pressure element creates a contact pressure force (F) acting on a sub-portion 36 of a bond wire portion configured between two adjacent bond sites. The contact pressure force (F) results in the power semiconductor chip and a substrate beneath being pressed against the heatsink.

Abstract: A semiconductor device capable of improving the driving power and a manufacturing method therefor are provided. In a semiconductor device, a gate structure formed by successively stacking a gate oxide film and a silicon layer is arranged over a semiconductor substrate. An oxide film is arranged long the lateral side of the gate structure and another oxide film is arranged along the lateral side of the oxide film and the upper surface of the substrate. In the side wall oxide film comprising these oxide films, the minimum value of the thickness of the first layer along the lateral side of the gate structure is less than the thickness of the second layer along the upper surface of the substrate.

Abstract: An optical sensing device includes a silicon-on-insulator (SOI) substrate a semiconductor support substrate, an insulating layer located on the semiconductor support substrate, and a semiconductor layer located on the insulating layer. The optical sensing device further includes a visible light sensor located in the semiconductor support substrate, and an ultraviolet ray sensor located in the semiconductor layer.