Abstract: Plating stub resonance in a circuit board may be mitigated by increasing surface roughness of the plating stub conductor. Roughening the plating stub increases its resistance due to the skin effect at higher frequencies, which decreases the quality factor of the transmission line and consequently increases the damping factor, to reduce any resonance that would occur in the plating stub as formed prior to roughening. The surface roughness can be increased in a variety of ways, including chemical processes, by selectively applying a laser beam, or by applying an etch-resistance material in selected locations.

Abstract: Interconnect structures and methods are disclosed. In one embodiment, an interconnect structure includes a via extendable through a workpiece from a first side of the workpiece to a second side of the workpiece. The via is partially filled with a conductive material and has sidewalls. The interconnect structure includes a contact coupled to the conductive material in the via proximate the first side of the workpiece. The conductive material in the via comprises a recessed region comprising a landing zone proximate the second side of the workpiece.

Abstract: A deposition apparatus configured to form a thin film on a substrate includes: a reactor wall; a substrate support positioned under the reactor wall; and a showerhead plate positioned above the substrate support. The showerhead plate defines a reaction space together with the substrate support. The apparatus also includes one or more gas conduits configured to open to a periphery of the reaction space at least while an inert gas is supplied therethrough. The one or more gas conduits are configured to supply the inert gas inwardly toward the periphery of the substrate support around the reaction space. This configuration prevents reactant gases from flowing between a substrate and the substrate support during a deposition process, thereby preventing deposition of an undesired thin film and impurity particles on the back side of the substrate.

Abstract: A semiconductor light-emitting device including a substrate, an n-type semiconductor layer formed on the substrate, an active layer laminated on the n-type semiconductor layer and capable of emitting a light, a p-type semiconductor layer laminated on the active layer, an n-electrode which is disposed on a lower surface of the semiconductor substrate or on the n-type semiconductor layer and spaced away from the active layer and p-type semiconductor layer, and a p-electrode which is disposed on the p-type semiconductor layer and includes a reflective ohmic metal layer formed on the dot-like metallic layer, wherein the light emitted from the active layer is extracted externally from the substrate side.

Abstract: A turbine rotor blade with a 3-pass serpentine flow cooling channel having a first leg located at the leading edge of the airfoil and a third leg located adjacent to the trailing edge of the airfoil and connected to a row of exit slots, and in which a second leg includes three separate channels in parallel with inlet metering holes to regulate a cooling air flow and pressure in each separate channel. The blade includes a blade tip channel connected to the first leg of the serpentine and which supplies the cooling air to the second leg channels through the separate metering holes. Because the metering holes can be sized individually, the hottest part of the mid-chord region of the airfoil can be supplied with more cooling air flow and the pressure ratio across the trailing edge can be reduced so that the exit slots can be larger or more numerous.

Abstract: A light emitting device manufacturing method including the steps of corrugatedly scanning a laser beam along a plurality of division lines formed on a light emitting device wafer having a sapphire substrate layer and a light emitting layer to apply the laser beam to the sapphire substrate layer, thereby performing laser processing for the sapphire substrate layer and next applying an external force to a processed locus formed along each division line by the above laser processing to thereby divide the light emitting device wafer into a plurality of light emitting devices. The sapphire layer of each light emitting device has side surfaces whose horizontal sectional shape is a corrugated shape. Accordingly, the number of total reflections on the side surfaces of the sapphire layer can be reduced to thereby achieve efficient emergence of light from the sapphire layer.

Abstract: In a method of forming a conductive layer structure and a method of manufacturing a recess channel transistor, a first insulating layer and a first conductive layer are sequentially formed on a substrate having a first region a second region and the substrate is exposed in a recess-forming area in the first region. A recess is formed in the recess-forming-area by etching the exposed region of the substrate. A second insulating layer is conformally formed on a sidewall and a bottom of the recess. A second conductive layer pattern is formed on the second insulating layer to fill up a portion of the recess. A spacer is formed on the second conductive layer pattern and on the second insulating layer on the sidewall of the recess. A third conductive layer pattern is formed on the second conductive layer pattern and the spacer to fill up the recess.

Abstract: In a method of vacuum packaging a MEMS device, at least one MEMS device is attached on a substrate. A solder preform is printed on the substrate at the perimeter surrounding the substrate. A lid is attached to the solder preform wherein the lid provides a cavity enclosing the at least one MEMS device. A first reflowing step reflows the solder at a first temperature, partially sealing the lid/substrate interface and at the same time does the outgassing and baking procedure for the packaging. Flux is applied onto an outer ring of the solder preform and a second step reflows the solder at a second temperature, completely sealing the lid/substrate interface and providing a vacuum cavity enclosing the at least one MEMS device.

Abstract: In one aspect provides a method of manufacturing a semiconductor device having improved transistor performance. In one aspect, this improvement is achieved by conducting a pre-deposition spacer deposition process wherein a temperature of a bottom region of a furnace is higher than a temperature of in the top region and is maintained for a predetermined period. The pre-deposition temperature is changed to a deposition temperature, wherein a temperature of the bottom region is lower than a temperature of the top region.

Abstract: A method of fabricating a semiconductor device is provided. A gate structure is formed on a substrate and then a first spacer is formed at a sidewall of the gate structure. Next, recesses are respectively formed in the substrate at two sides of the first spacer. Thereafter, a buffer layer and a doped semiconductor compound layer are formed in each recess. An extra implantation region is respectively formed on the surfaces of each buffer layer and each doped semiconductor compound layer. Afterward, source/drain contact regions are formed in the substrate at two sides of the gate structure.

Abstract: A method and apparatus for breaking a semiconductor substrate along a predetermined area over which a split groove is formed. The breaking apparatus includes a table for placing a portion of the semiconductor substrate inside the predetermined area and a breaking blade being operable to move downward from a position above the semiconductor substrate placed on the table to thereby compress a portion of the semiconductor substrate outside the predetermined area so that the semiconductor substrate is broken along the split groove. The predetermined area of the semiconductor substrate has at least a neighboring pair of sides intersecting at an angle of less than 180 degrees, and the breaking blade has a projection which, when the semiconductor substrate is broken, compresses a portion of the semiconductor substrate outside the one side so that the one side is compressed ahead of the other side.

Abstract: An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over said silicon substrate, a first interconnecting structure in said dielectric structure, a first pad connected to said first node of said voltage regulator through said first interconnecting structure, a second interconnecting structure in said dielectric structure, a second pad connected to said first node of said internal circuit through said second interconnecting structure, a passivation layer over said dielectric structure, wherein multiple opening in said passivation layer exposes said first and second pads, and a third interconnecting structure over said passivation layer and over said first and second pads.

Abstract: A semiconductor device having reduced input capacitance is disclosed. The semiconductor device includes a pedestal region having a gate overlying a sidewall of the pedestal region and gate interconnect overlying a major surface of the pedestal region. The pedestal region includes a conductive shield layer (260). The conductive shield layer (260) is isolated from the gate of the transistor by more than one dielectric layer (330, 340, and 350) to reduce input capacitance. The pedestal region includes an air gap region (1525) to further lower the dielectric constant of the pedestal region between the gate/gate interconnect and the conductive shield layer (260).

Abstract: A vertical GaN-based LED comprises an n-electrode; an n-type GaN layer formed under the n-electrode, the n-type GaN layer having an irregular-surface structure which includes a first irregular-surface structure having irregularities formed at even intervals and a second irregular-surface structure having irregularities formed at uneven intervals, the second irregular-surface structure being formed on the first irregular-surface structure; an active layer formed under the n-type GaN layer; a p-type GaN layer formed under the active layer; a p-electrode formed under the p-type GaN layer; and a structure support layer formed under the p-electrode.

Abstract: Semiconductor workpiece carriers and methods for processing semiconductor workpieces are disclosed herein. In one embodiment, a semiconductor workpiece carrier assembly includes (a) a support structure having an opening sized to receive at least a portion of a semiconductor workpiece, and (b) a replaceable carrier positioned at the opening. The replaceable carrier includes a base and an adhesive layer on the base. The base has a surface, and the adhesive layer covers only a section of the surface of the base. The adhesive layer releasably attaches the replaceable carrier to the support structure.

Abstract: A semiconductor device is provided which comprises a substrate (501) having a plurality of bond pads (503) disposed thereon. Each bond pad has a major axis and a minor axis in a direction parallel to the substrate, and the ratio of the major axis to the minor axis increases with the distance of a bond pad from the center of the substrate.

Abstract: A method for fabricating a sensor is disclosed that in one embodiment bonds a first device wafer to an etched second device wafer to create a suspended structure, the flexure of which is determined by an embedded sensing element that is in electrical communication with an outer surface of the sensor through an interconnect embedded in a device layer of the first device wafer. In one embodiment the suspended structure is enclosed by a cap and the sensor is configured to measure absolute pressure.

Abstract: A method for patterning crystalline indium tin oxide (ITO) using femtosecond laser is disclosed, which comprises steps of: (a) providing a substrate with an amorphous ITO layer thereon; (b) transferring the amorphous ITO layer in a predetermined area into a crystalline ITO layer by emitting a femtosecond laser beam to the amorphous ITO layer in the predetermined area; and (c) removing the amorphous ITO layer on the substrate using an etching solution.

Abstract: A tube is arranged to be in contact with an insulating layer in an opening formation region, and a treatment agent (etching gas or etchant) is discharged to the insulating layer through the tube. With the discharged treatment agent (etching gas or etchant), the insulating layer is selectively removed to form an opening in the insulating layer. Therefore, the insulating layer provided with the opening is formed over a first conductive layer, and the first conductive layer below the insulating layer is exposed at the bottom of the opening. A second conductive layer is formed in the opening to be in contact with an exposed part of the first conductive layer, so that the first conductive layer and the second conductive layer are electrically connected in the opening provided in the insulating layer.

Abstract: Methods for manufacturing thin film transistor arrays utilizing three steps of lithography and one step of laser ablation while the lithography procedure is used four to five times in conventional processes are disclosed. The use of the disclosed methods assists in improving throughput and saving of manufacturing cost.