Abstract: Embodiments of a silicon heat-dissipation package for compact electronic devices are described. In one aspect, a device includes first and second silicon cover plates. The first silicon cover plate has a first primary side and a second primary side opposite the first primary side thereof. The second silicon cover plate has a first primary side and a second primary side opposite the first primary side thereof. The first primary side of the second silicon cover plate includes an indentation configured to accommodate an electronic device therein. The first primary side of the second silicon cover plate is configured to mate with the second primary side of the first silicon cover plate when the first silicon cover plate and the second silicon cover plate are joined together with the electronic device sandwiched therebetween.

Abstract: A quad flat no lead (“QFN”) package that includes a die having an active side positioned substantially in a first plane and a backside positioned substantially in a second plane parallel to the first plane; a plurality of separate conductive pads each having a first side positioned substantially in the first plane and a second side positioned substantially in the second plane; and mold compound positioned between the first and second planes in voids between the conductive pads and the dies. Also a method of producing a plurality of QFN packages includes forming a strip of plastic material having embedded therein a plurality of dies and a plurality of conductive pads that are wire bonded to the dies and singulating the strip into a plurality of QFN packages by cutting through only the plastic material.

Abstract: A leadframe including a metal oxide layer on at least a portion of the leadframe are disclosed. More specifically, leadframes with a metal layer and a metal oxide layer formed on one or more leads before a tin finish plating layer is formed are described. The layers of metal and metal oxide between the one or more leads and the tin finish plating layer reduce the formation of tin whiskers, thus reducing the likelihood of shorting and improving the overall reliability of the package structure and device produced.

Abstract: A semiconductor package includes: a first substrate; a semiconductor chip mounted on the first substrate such that a circuit formation surface is oriented toward the first substrate; a second substrate arranged above the first substrate, the semiconductor chip being sandwiched between the first substrate and the second substrate; and a resin that seals the semiconductor chip and that is filled between the first substrate and the second substrate, wherein the second substrate includes a solder resist layer having a first surface facing a back surface that is an opposite surface of the circuit formation surface of the semiconductor chip, and wherein on an area of the first surface of the solder resist layer facing the back surface of the semiconductor chip, at least one protruding portion that protrudes towards the back surface of the semiconductor chip is provided.

Abstract: Semiconductor packages having a sealant bridge between an integrated heat spreader and a package substrate are described. In an embodiment, a semiconductor package includes a sealant bridge anchoring the integrated heat spreader to the package substrate at locations within an overhang gap laterally between a semiconductor die and a sidewall of the integrated heat spreader. The sealant bridge extends between a top wall of the integrated heat spreader and a die side component, such as a functional electronic component or a non-functional component, or a satellite chip on the package substrate. The sealant bridge modulates warpage or stress in thermal interface material joints to reduce thermal degradation of the semiconductor package.

Abstract: A semiconductor package includes a die pad having a die attach surface, a first laterally separated and vertically offset from the die pad, a semiconductor die mounted on the die attach surface and comprising a first terminal on an upper surface of the semiconductor die, an interconnect clip that is electrically connected to the first terminal and to the first lead, and a heat spreader mounted on top of the interconnect clip. The interconnect clip includes a first planar section that interfaces with the upper surface of the semiconductor die and extends past an outer edge side of the die pad. The heat spreader covers an area of the first planar section that is larger than an area of the semiconductor die. The heat spreader laterally extends past a first outer edge side of the die pad that faces the first lead.

Abstract: A power semiconductor apparatus includes a mold portion, a panel that is conductive and in a flat plate shape, and a plurality of fins. The mold portion includes a power semiconductor element and a base plate that are molded. An opening is formed in the panel into which the base plate is inserted. The plurality of fins is fixed in grooves of the base plate. The panel has a plurality of protrusions on side surfaces forming the opening. Each protrusion has a fifth surface a cross section of which has a shape that tapers down toward an end of the protrusion, the cross section being parallel to a plane extending in the Z direction and a direction in which the protrusion protrudes. The base plate has cover portions covering the fifth surfaces, and is plastically deformed to allow the panel to be fitted in the base plate to fill gaps.

Abstract: One embodiment provides a method of providing a power semiconductor module with a cooler. A power semiconductor module includes a substrate having a first substrate side for carrying at least one electric circuit and having a second substrate side being located opposite to the first substrate side. The second substrate side is connected to a first baseplate side and the baseplate also includes a second baseplate side being located opposite to its first baseplate side and being adapted for coming in contact with the cooler. The cooler includes a first casing component and a second casing component. The baseplate side is equipped with a cooling area that is surrounded by a connecting area.

Abstract: A guard ring structure includes a plurality of first groups of concentric guard rings encompassing an active region of an integrated circuit, the concentric guard rings of the first groups having a guard ring pitch of less than 80 nm. The concentric guard rings of the first groups have a single, closed path that is distinct from an adjacent guard ring and defines a rectangular geometry with rounded corners. Second groups of guard rings are interspersed with and concentrically arranged with the first groups, where each corner region of the second groups include at least one guard ring defect. A method of fabricating a guard ring structure for an integrated circuit is also disclosed.

Abstract: A mold chase for packaging a compartmentally shielded multifunctional semiconductor is provided. The mold chase generally includes a first cavity and a second cavity separated by a trench plate positioned between a first component and a second component of the multifunctional semiconductor between which a compartmental shield is required. The mold chase is lowered into a molding position over the multifunctional semiconductor and a molding material is injected through an inlet sprue into the first and second cavities to surround the first and second components, respectively. After the molding material is cured, the mold chase is removed and an open trench is formed in the cured molding material by the trench plate. The open trench is filled with a conductive material to form the compartmental shield. A conformal shield may be added to cover the package.

Abstract: Described is a packaged component having a first surface and an opposite second surface. The packaged component may comprise a first element a second element, and a third element. The first element may have a first surface and an opposite second surface. The second element may have a first surface and an opposite second surface. The third element may electrically connect a portion of the first element to a portion of the second element. The second surface of the first element may be adjacent to the second surface of the packaged component, and the second surface of the second element may be adjacent to the second surface of the packaged component.

Abstract: A semiconductor device in which a semiconductor element mounted on a laminate substrate and an electrically conductive connection member are sealed with a sealing material, includes: a primer layer in an interface between the sealing material and sealed members including the laminate substrate, the semiconductor element, and the electrically conductive connection member, in which the sealing material includes a first sealing layer which is provided in contact with the primer layer; and a second sealing layer which covers the first sealing layer, the semiconductor device satisfies ?p??1>?2 in which ?p, ?1, and ?2 represent coefficients of linear thermal expansion of the primer layer, the first sealing layer, and the second sealing layer, respectively, ?c?15×10?6/° C. in which ?c represents a composite coefficient of linear thermal expansion of the sealing layers, and Ec?5 GPa or more in which Ec represents a composite Young's modulus of the sealing layers.

Abstract: A method for mounting an electrical component on a substrate is disclosed. According to the method, joining is simplified using a cover, or hood, that includes a contact structure on an inner side of the hood, wherein when the hood is mounted, the contact structure is joined to the underlying structure at different joining levels simultaneously using an additional material. Moreover, a joining pressure, e.g., for diffusion or sintered bonds for electrical contacts, can be applied using such a hood.

Abstract: A method embodiment includes forming a patterned first photo resist over a seed layer. A first opening in the patterned first photo resist exposes the seed layer. The method further includes plating a first conductive material in the first opening on the seed layer, removing the patterned first photo resist, and after removing the patterned first photo resist, forming a patterned second photo resist over the first conductive material. A second opening in the patterned second photo resist exposes a portion of the first conductive material. The method further includes plating a second conductive material in the second opening on the first conductive material, removing the patterned second photo resist, and after removing the patterned second photo resist, depositing a dielectric layer around the first conductive material and the second conductive material.

Abstract: A manufacturing method of a mounting structure, the method including: a step of preparing a mounting member including a first circuit member and a plurality of second circuit members placed on the first circuit member via bumps, the mounting member having a space between the first circuit member and the second circuit member; a step of preparing a sheet having a space maintaining layer; a disposing step of disposing the sheet on the mounting member such that the space maintaining layer faces the second circuit members; and a sealing step of pressing the sheet against the first circuit member and heating the sheet, to seal the second circuit members so as to maintain the space, and to cure the sheet. The bumps are solder bumps. The space maintaining layer after curing has a glass transition temperature of higher than 125° C., and a coefficient of thermal expansion at 125° C. or lower of 20 ppm/K or less.

Abstract: An electronic component whose reliability is less likely to decrease while its thermal conductivity is maintained. A semiconductor chip is mounted on a substrate. The semiconductor chip is sealed with a sealing resin layer. The sealing resin layer includes a binder and two types of fillers having a plurality of particles dispersed in the binder. As the two types of fillers, fillers at least one of whose physical quantities, which are average particle diameter and density, are different from each other are used. The total volume density of the fillers in the sealing resin layer decreases in an upward direction from the substrate, and a portion of the sealing resin layer in a height direction of the sealing resin layer has an area in which the two types of fillers are present in a mixed manner.

Abstract: In an assembly in which a space between two elements is filled with a filler containing resin, a configuration that can limit both the size of the assembly and the cost of the fillers is provided. Assembly 10 of stacked elements has: first element 2 having first surface 21; resin layer 61 that is arranged on first surface 21 and that contains a plurality of fillers F; and second element 4 that is arranged on resin layer 61 and that has second surface 41 that is in contact with resin layer 61. In a section that is perpendicular to second surface 41, the average flattening ratio of fillers F2 that are in contact with second surface 41 is larger than the average flattening ratio of fillers F1, F3 that are not in contact with second surface 41. Here, the flattening ratio is a ratio of the maximum length of the filler in a direction parallel to second surface 41 to the maximum thickness of the filler in a direction perpendicular to second surface 41.

Abstract: A semiconductor device according to an embodiment is attached to a radiator and includes a heat-generating electronic component, a sealing part sealing the electronic component, a lead member that includes an inner lead part sealed with the sealing part and an outer lead part exposed from the sealing part, and a lead member that includes an inner lead part sealed with the sealing part and an outer lead part exposed from the sealing part. The inner lead part has a heat-dissipating end part that releases heat propagating from the outer lead part to the radiator and an electrical connecting part that is positioned between the heat-dissipating end part and the outer lead part and is electrically connected to the main electrode of the electronic component.

Abstract: A semiconductor device, includes: a semiconductor element including an element main surface and an element back surface facing opposite sides in a thickness direction; a wiring part electrically connected to the semiconductor element; an electrode pad electrically connected to the wiring part; a sealing resin configured to cover a part of the semiconductor element; and a first metal layer configured to make contact with the element back surface and exposed from the sealing resin, wherein the semiconductor element overlaps the first metal layer when viewed in the thickness direction.

Abstract: A semiconductor memory device includes a substrate, gate electrodes arranged in a thickness direction of the substrate, first and second semiconductor layers, a gate insulating film, and a first contact. The first semiconductor layer extends in the thickness direction and faces the gate electrodes. The gate insulating film is between the gate electrodes and the first semiconductor layer. The second semiconductor layer is between the substrate and the gate electrodes and connected to a side surface of the first semiconductor layer in a surface direction. The first contact extends in the thickness direction and electrically connected to the second semiconductor layer. The second semiconductor layer includes a first region in contact with the side surface of the first semiconductor layer and containing P-type impurities, and a first contact region electrically connected to the first contact and having a higher concentration of N-type impurities than the first region.