Abstract: A fan-out semiconductor package may include: a first connection member having a through hole; a semiconductor chip disposed in the through hole and having an active surface on which a connection pad is disposed and a non-active surface opposing the active surface; an encapsulant at least partially encapsulating the first connection member and the non-active surface of the semiconductor chip; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad, wherein the first connection member includes a first insulating layer, a first redistribution layer embedded in the first insulating layer while contacting the second connection member, and a second redistribution layer disposed on the other side of the first insulating layer opposing one side thereof in which the first redistribution layer is embedded.

Abstract: An embodiment is a structure including a first die, a molding compound at least laterally encapsulating the first die, a first redistribution structure including metallization patterns extending over the first die and the molding compound, a first conductive connector comprising a solder ball and an under bump metallization coupled to the first redistribution structure, and an integrated passive device bonded to a first metallization pattern in the first redistribution structure with a micro bump bonding joint, the integrated passive device being adjacent the first conductive connector.

Abstract: The present disclosure is directed to a die having a metallized sidewall and methods of manufacturing the same. A contiguous metal layer is applied to each edge of a backside of a wafer. The wafer is cut at a base of a plurality of channels formed in the backside to create individual die each having a flange that is part of a sidewall of the die and includes a portion that is covered by the metal layer. When an individual die is coupled to a die pad, a semiconductive glue bonds the metal layer on the sidewall and a backside of the die to the die pad, which decreases the risk of delamination along the sides of the die. The flange also prevents the glue from contacting the active side of the die by acting as a barrier against adhesive creep of the glue up the sidewall of the die.

Abstract: A component includes a carrier having a front side facing towards a semiconductor body and a rear side facing away from the semiconductor body, each of which is formed at least in places by a surface of a shaped body, a metal layer contains a first sub-region and a second sub-region, wherein the first sub-region and the second sub-region adjoin the shaped body in a lateral direction, are electrically connectable in a vertical direction on the front side of the carrier, are assigned to different electrical polarities of the component and are thus configured to electrically contact the semiconductor body, and the carrier has a side face running perpendicularly or obliquely to the rear side of the carrier and is configured as a mounting surface of the component, wherein at least one of the sub-regions is electrically connectable via the side face and exhibits singulation traces.

Abstract: This application discloses a flexible substrate device that includes a flexible substrate and a plurality of electronic devices. The flexible substrate includes a top surface and a bottom surface opposite to the top surface, and the plurality of electronic devices formed on the top surface of the flexible substrate. The bottom surface further includes one or more strong adhesion regions and one or more normal adhesion regions that are distinct from the one or more strong adhesion regions. Each of the one or more strong adhesion regions and the one or more normal adhesion regions are configured to attach to a rigid carrier with first adhesion strength and second adhesion strength, respectively. The first adhesion strength is substantially larger than the second adhesion strength. In some embodiments, the flexible substrate device is a thin film transistor (TFT) device, and the plurality of electronic devices includes a TFT array.

Abstract: In various embodiments, a method for processing a semiconductor wafer is provided. The semiconductor wafer includes a first main processing side and a second main processing side, which is arranged opposite the first main processing side, and at least one circuit region having at least one electronic circuit on the first main processing side. The method includes forming a stiffening structure, which at least partly surrounds the at least one circuit region and which stiffens the semiconductor wafer, wherein the stiffening structure has a cutout at least above part of the at least one circuit region, and thinning the semiconductor wafer, including the stiffening structure, from the second main processing side.

Abstract: A package structure is provided. The package structure includes a molding compound. The package structure also includes an integrated circuit chip having a chip edge in the molding compound. The package structure further includes a passivation layer below the integrated circuit chip and the molding compound. In addition, the package structure includes a redistribution layer in the passivation layer. The package structure also includes first bumps electrically connected to the integrated circuit chip through the redistribution layer. The first bumps are inside the chip edge and arranged along the chip edge. The package structure further includes second bumps electrically connected to the integrated circuit chip through the redistribution layer. The second bumps are outside the chip edge and arranged along the chip edge. The first bumps are next to the second bumps. The first and second bumps are spaced apart from the chip edge.

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first carrier substrate having a first surface and an opposing second surface. A second carrier substrate is stacked on the first carrier substrate and has a first surface and an opposing second surface that faces the first surface of the first carrier substrate. A semiconductor die is mounted on the first surface of the second carrier substrate. A heat spreader is disposed on the first surface of the first carrier substrate to cover and surround the second carrier substrate and the semiconductor die. A method for forming the semiconductor package structure is also provided.

Abstract: A power semiconductor package has a small footprint. A preparation method is used to fabricate the power semiconductor package. A first semiconductor chip and a second semiconductor chip are attached to a front side and a back side of a die paddle respectively. Conductive pads are then attached to electrodes at top surfaces of the first and second semiconductor chips. It is followed by a formation of a plastic package body covering the die paddle, the first and second semiconductor chips, and the conductive pads. Side surfaces of the conductive pads are exposed from a side surface of the plastic package body.

Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first insulating layer is formed over a first surface of the encapsulant and an active surface of the semiconductor die. A second insulating layer is formed over a second surface of the encapsulant opposite the first surface. A conductive layer is formed over the first insulating layer. The conductive layer includes a line-pitch or line-spacing of less than 5 ?m. The active surface of the semiconductor die is recessed within the encapsulant. A third insulating layer is formed over the semiconductor die including a surface of the third insulating layer coplanar with a surface of the encapsulant. The second insulating layer is formed prior to forming the conductive layer. A trench is formed in the first insulating layer. The conductive layer is formed within the trench.

Abstract: A semiconductor device comprises a first semiconductor package including a conductive layer. A substrate including an interconnect structure is disposed over the conductive layer. The interconnect structure of the substrate with the conductive layer of the first semiconductor package are self-aligned. A plurality of openings is formed in the substrate. An adhesive is disposed between the substrate and the first semiconductor package and in the openings of the substrate. A redistribution layer (RDL) is formed over the first semiconductor package opposite the substrate. A pitch of the substrate is different from a pitch of the RDL. The adhesive extends to the interconnect structure of the substrate. A second semiconductor package is disposed over the substrate and the first semiconductor package.

Abstract: A method of manufacturing a semiconductor device includes providing an electrically conductive carrier and placing a semiconductor chip over the carrier. The method includes applying an electrically insulating layer over the carrier and the semiconductor chip. The electrically insulating layer has a first face facing the carrier and a second face opposite to the first face. The method includes selectively removing the electrically insulating layer and applying solder material where the electrically insulating layer is removed and on the second face of the electrically insulating layer.

Abstract: A method for manufacturing an electronic component can include the following steps: providing a semiconductor arrangement comprising a carrier structure which has at least one semiconductor chip incorporated into a potting compound, and a redistribution layer which comprises a flexible material and at least one strip conductor, wherein the carrier structure at least in regions is connected to the redistribution layer, and the at least one semiconductor chip is electrically conductively connected to the redistribution layer, and separating the carrier structure along at least one trench in a manner such that the carrier structure is divided into at least two singularized carrier elements, wherein two adjacent ones of the singularized carrier elements are connected to one another over the respective trench by way of the redistribution layer.

Abstract: A semiconductor device has a temporary layer, such as a dam material or adhesive layer, formed over a carrier. A plurality of recesses is formed in the temporary layer. A first semiconductor die is mounted within the recesses of the temporary layer. An encapsulant is deposited over the first semiconductor die and temporary layer. The encapsulant extends into the recesses in the temporary layer. The carrier and temporary layer are removed to form recessed interconnect areas around the first semiconductor die. Alternatively, the recessed interconnect areas can be formed the carrier or encapsulant. Multiple steps can be formed in the recesses of the temporary layer. A conductive layer is formed over the first semiconductor die and encapsulant and into the recessed interconnect areas. A second semiconductor die can be mounted on the first semiconductor die. The semiconductor device can be integrated into PiP and Fi-PoP arrangements.

Abstract: A display device comprises: a display panel; a metallic wiring formed in the display panel; and a semiconductor integrated circuit element connected to the display panel through a UV curing anisotropy conductive film, wherein the semiconductor integrated circuit element includes a plurality of bumps, the metallic wiring is electrically connected to the bumps through the UV curing anisotropy conductive film, the metallic wiring includes a plurality of openings, and at least one of the bumps is disposed between two adjacent openings closest to each other in the plurality of openings.

Abstract: A method embodiment includes forming a patterned first photo resist over a seed layer. A first opening in the patterned first photo resist exposes the seed layer. The method further includes plating a first conductive material in the first opening on the seed layer, removing the patterned first photo resist, and after removing the patterned first photo resist, forming a patterned second photo resist over the first conductive material. A second opening in the patterned second photo resist exposes a portion of the first conductive material. The method further includes plating a second conductive material in the second opening on the first conductive material, removing the patterned second photo resist, and after removing the patterned second photo resist, depositing a dielectric layer around the first conductive material and the second conductive material.

Abstract: A customized seal ring for a semiconductor device is formed of multiple seal ring cells that are selected and arranged to produce a seal ring design. The cells include first cells that are coupled to ground and second cells that are not coupled to ground. The second cells that are not coupled to ground, include a higher density of metal features in an inner portion thereof, than the first seal ring cells. Dummy metal vias and other metal features that may be present in the inner portion of the second seal ring cells are absent from the inner portion of the first seal ring cells that are coupled to ground. The seal ring design may include various arrangements, including alternating and repeating sequences of the different seal ring cells.

Abstract: Micro pillars are formed in silicon. The micro pillars are used in boding the silicon to hetero-material such as III-V material, ceramics, or metals. In bonding the silicon to the hetero-material, indium is used as a bonding material and attached to the hetero-material. The bonding material is heated and the silicon and the hetero-material are pressed together. As the silicon and the hetero-material are pressed together, the micro pillars puncture the bonding material. In some embodiments, pedestals are used in the silicon as hard stops to align the hetero-material with the silicon.

Abstract: Composite heat sink structures and methods of fabrication are provided, with the composite heat sink structures including: a thermally conductive base having a main heat transfer surface to couple to, for instance, at least one electronic component to be cooled; a compressible, continuous sealing member; and a sealing member retainer compressing the compressible, continuous sealing member against the thermally conductive base; and an in situ molded member. The in situ molded member is molded over and affixed to the thermally conductive base, and is molded over and secures in place the sealing member retainer. A coolant-carrying compartment resides between the thermally conductive base and the in situ molded member, and a coolant inlet and outlet are provided in fluid communication with the coolant-carrying compartment to facilitate liquid coolant flow through the compartment.

Abstract: A conductive connecting member formed on a bonded face of an electrode terminal of a semiconductor or an electrode terminal of a circuit board, the conductive connecting member comprising a porous body formed in such manner that a conductive paste containing metal fine particles (P) having mean primary particle diameter from 10 to 500 nm and an organic solvent (S), or a conductive paste containing the metal fine particles (P) and an organic dispersion medium (D) comprising the organic solvent (S) and an organic binder (R) is heating-treated so as for the metal fine particles (P) to be bonded, the porous body being formed by bonded metal fine particles (P) having mean primary particle diameter from 10 to 500 nm, a porosity thereof being from 5 to 35 volume %, and mean pore diameter being from 1 to 200 nm.