Abstract: A semiconductor device may be provided with: a semiconductor chip; an encapsulant encapsulating the semiconductor chip therein; and a conductor member joined to the semiconductor chip via a solder layer within the encapsulant. The conductor member may comprise a joint surface in contact with the solder layer and a side surface extending from a peripheral edge of the joint surface. The side surface may comprise an unroughened area and a roughened area that is greater in surface roughness than the unroughened area. The unroughened area may be located adjacent to the peripheral edge of the joint surface.

Abstract: Provided is a sealing structure including a housing that houses a heat generating member or a heat dissipation member thereinside, and a resin that is filled in the housing. In a sectional view, the housing includes a first recess portion in a position facing the heat generating member or the heat dissipation member.

Abstract: An integrated circuit product includes a first layer of insulating material including a first insulating material. The first layer of insulating material is positioned above a device layer of a semiconductor substrate. The device layer includes transistors. A metallization blocking structure is positioned in an opening in the first layer of insulating material. The metallization blocking structure includes a second insulating material that is different from the first insulating material. A metallization trench is defined in the first layer of insulating material on opposite sides of the metallization blocking structure. A conductive metallization line includes first and second portions positioned in the metallization trench on opposite sides of the metallization blocking structure. The conductive metallization line has a long axis extending along the first and second portions.

Abstract: One or more embodiments are related to a semiconductor device, comprising: a metallization layer comprising a plurality of portions, each of the portions having a different thickness. The metallization layer may be a final metal layer.

Abstract: A semiconductor device includes a base member, a multilayer wiring layer, and a first resistive element. The multilayer wiring layer is formed on the base member. The first resistive element is formed in the multilayer wiring layer. The first resistive element includes a first conductive part, a second conductive part and a third conductive part. The second conductive part is formed over the first conductive part. The third conductive part electrically connects the first conductive part and the second conductive part with each other. A length of the third conductive part in a first direction along a surface of the base member is greater than a length of the third conductive part in a second direction along the surface of the base member and perpendicular to the first direction.

Abstract: Integrated chips and methods of forming the same include forming upper dummy lines over lower conductive lines. The lower conductive lines are recessed to form conductive vias between the lower conductive lines and the upper dummy lines. The upper dummy lines are replaced with upper conductive lines that contact the conductive vias.

Abstract: A semiconductor device comprises a first semiconductor package including a conductive layer. A substrate including an interconnect structure is disposed over the conductive layer. The interconnect structure of the substrate with the conductive layer of the first semiconductor package are self-aligned. A plurality of openings is formed in the substrate. An adhesive is disposed between the substrate and the first semiconductor package and in the openings of the substrate. A redistribution layer (RDL) is formed over the first semiconductor package opposite the substrate. A pitch of the substrate is different from a pitch of the RDL. The adhesive extends to the interconnect structure of the substrate. A second semiconductor package is disposed over the substrate and the first semiconductor package.

Abstract: A termination opening can be formed through the stack alternating dielectrics concurrently with forming contact openings through the stack. A termination structure can be formed in the termination opening. An additional opening can be formed through the termination structure and through the stack between groups of semiconductor structures that pass through the stack. In another example, an opening can be formed through the stack so that a first segment of the opening is between groups of semiconductor structures in a first region of the stack and a second segment of the opening is in a second region of the stack that does not include the groups of semiconductor structures. A material can be formed in the second segment so that the first segment terminates at the material. In some instances, the material can be implanted in the dielectrics in the second region through the second segment.

Abstract: Methods of patterning openings for conductive contacts in a target layer of a semiconductor device and methods of forming conductive contacts. The method of patterning openings may be used to form contact openings in an inter-layer dielectric (ILD) layer of a semiconductor substrate for contacts to source/drain regions of FinFET devices. A hard mask layer may be patterned to form a cut mask by transferring slotted openings of a first middle layer of a tetra-layer photoresist and a cut MD pattern of a photoresist layer formed over the first middle layer of the tetra-layered photoresist using photolithography techniques. Once the cut mask is formed, contact openings are formed within the ILD layer down to the source/drain regions of the FinFET devices of the semiconductor substrate. The contact openings may be filled with conductive material(s) to define conductive contacts (e.g., conductive plugs).

Abstract: A floating gate fabrication method is disclosed. The method includes: providing a substrate, and depositing an oxide layer on the substrate; fabricating a shallow trench isolation in the substrate, a top surface of the shallow trench isolation being higher than a top surface of the oxide layer; depositing a polysilicon layer on the oxide layer and the shallow trench isolation; performing a first thermal annealing process on the polysilicon layer, thereby repairing cavities formed after the deposition of the polysilicon layer; implanting ions into the polysilicon layer; performing a second thermal annealing process on the polysilicon layer, thereby activating the implanted ions and repairing again the cavities formed after the deposition of the polysilicon layer; and planarizing the polysilicon layer to form a floating gate.

Abstract: A method of forming a pattern of metallic material on a substrate includes providing a plurality of void regions on a surface of the substrate. At a first temperature, a first layer of a first metallic material of a eutectic-forming pair of metallic materials is deposited on the substrate to form a conformal metallic film over the substrate and over the surfaces of the plurality of void regions. The substrate and conformal metallic film are warmed to a second temperature greater than a eutectic-liquid-formation temperature of the eutectic pair of metallic materials. At the second temperature, the second metallic material of the eutectic-forming pair of metallic materials is deposited on the conformal metallic film to initiate a eutectic-liquid-forming reaction, such that the plurality of void regions are filled with a mixture of the first and second metallic materials of the eutectic-forming pair of metallic materials.

Abstract: A method of manufacturing a device in a semiconductor body includes forming a first field stop zone portion of a first conductivity type and a drift zone of the first conductivity type on the first field stop zone portion. An average doping concentration of the drift zone is smaller than 80% of that of the first field stop zone portion. The semiconductor body is processed at a first surface and thinned by removing material from a second surface. A second field stop zone portion of the first conductivity type is formed by implanting protons at one or more energies through the second surface. A deepest end-of-range peak of the protons is set in the first field stop zone portion at a vertical distance to a transition between the drift zone and first field stop zone portion in a range from 3 ?m to 60 ?m. The semiconductor body is annealed.

Abstract: Method and apparatus for a capacitive structure. The capacitive structure includes a material stack having a deep trench formed therein. The material stack includes alternating vertical and semi-ovoid sidewall surfaces. The material stack further includes alternating metallization layers and dielectric layers. At least one of the semi-spheroidal sidewall surfaces is formed in a sidewall of at least one of the dielectric layers in the deep trench. At least one of the vertical sidewall surfaces is a sidewall surface of at least one metallization layer in the deep trench.

Abstract: A semiconductor device and a fabricating method of the same are provided. The semiconductor device a substrate including an active region defined by an element isolation film, an impurity region having a first conductivity type in the active region, a first semiconductor film of a second conductivity type on the impurity region, a buried insulating film on the first semiconductor film, a second semiconductor film on the buried insulating film, and a well contact connected to the first semiconductor film. The level of a lowermost surface of the first semiconductor film is higher than a level of a lowermost surface of the element isolation film.

Abstract: A method for fabricating an interposer substrate is provided, including forming a wiring layer on a carrier, forming an insulating layer on the carrier, forming on the wiring layer a wiring build-up layer structure that is electrically connected to the wiring layer, forming on the wiring build-up layer structure external connection pillars that are electrically connected to the wiring build-up layer structure, and removing the carrier, with the wiring layer is exposed from a surface of the insulating layer. The fabrication process of the via can be bypassed in the fabrication process by forming coreless interposer substrate on the carrier, such that the overall cost of the fabrication process can be decreased, and the fabrication process is simple. This invention further provides the interposer substrate.

Abstract: There is a need to improve reliability of the semiconductor device. A semiconductor device includes a printed circuit board and a semiconductor chip mounted over the printed circuit board. The semiconductor chip includes a pad, an insulation film including an opening to expose part of the pad, and a pillar electrode formed over the pad exposed from the opening. The printed circuit board includes a terminal and a resist layer including an opening to expose part of the terminal. The pillar electrode of the semiconductor chip and the terminal of the printed circuit board are coupled via a solder layer. Thickness h1 of the pillar electrode is measured from the upper surface of the insulation film. Thickness h2 of the solder layer is measured from the upper surface of the resist layer. Thickness h1 is greater than or equal to a half of thickness h2 and is smaller than or equal to thickness h2.

Abstract: A process for attaching a first substrate to a second substrate by direct bonding includes the successive steps of: a) providing the first and second substrates, each comprising a first surface and an opposite second surface, b) bonding the first substrate to the second substrate by direct bonding between the first surfaces of the first and second substrates, step b) being carried out under a first gaseous atmosphere having a first relative humidity level denoted by ?1, and c) applying a thermal annealing treatment to the bonded first and second substrates at a thermal annealing temperature of between 20° C. and 700° C., step c) being carried out under a second gaseous atmosphere having a second humidity level denoted by ?2, satisfying ?2??1.

Abstract: A power semiconductor device includes a casing, a first insulating circuit board, a second insulating circuit board, and a sealing material. The first insulating circuit board is disposed to be surrounded by the casing. The second insulating circuit board is surrounded by the casing and spaced from the first insulating circuit board so as to sandwich a semiconductor element between the first insulating circuit board and the second insulating circuit board. The sealing material fills a region surrounded by the casing. The first or second insulating circuit board is provided with a hole extending from one main surface to the other main surface opposite to one main surface. From at least a portion of an inner wall surface of the casing a protrusion extending to a region overlapping the first or second insulating circuit board in a plan view extends toward the region surrounded by the casing.

Abstract: A method is presented for reducing parasitic capacitance. The method includes forming multi-layer spacers between source/drain regions, forming a dielectric liner over the multi-layer spacers and the source/drain regions, forming gate structures adjacent the multi-layer spacers, forming a self-aligned contact cap over the gate structures, and removing a sacrificial layer of each of the multi-layer spacers to form air-gaps between the gate structures and the source/drain regions.

Abstract: A wafer-level chip-size package includes a semiconductor structure. A bonding pad is formed over the semiconductor structure, including a plurality of conductive segments. A conductive component is formed over the semiconductor structure, being adjacent to the bonding pad. A passivation layer is formed, exposing a portions of the conductive segments of the first bonding pad. A conductive redistribution layer is formed over the portions of the conductive segments of the first bonding pad exposed by the passivation layer. A planarization layer is formed over the passivation layer and the conductive redistribution layer, exposing a portion of the conductive redistribution layer. A UBM layer is formed over the planarization layer and the portion of the conductive redistribution layer exposed by the planarization layer. A conductive bump is formed over the UBM layer.