Abstract: The present invention relates to integrated circuit packaging useful for programmable logic devices. The invention provides a migration path between a base integrated circuit and an extended integrated circuit that is a functional superset of the base. In the case of a programmable logic device (PLD), the pin element layout for a base integrated circuit provides for the connection of power, control, and I/O signals. Pins conducting power signals are located at the core of the base pin layout. Pins conducting control signals are located near the intersections of the horizontal and vertical axes of the layout and the perimeter of the layout. Remaining pins conduct I/O signals. The pin element layout for an extended integrated circuit subsumes the base pin element layout. Additional pins for conducting power signals are located near one or more diagonal axes of the extended pin element layout.

Abstract: The method of the present invention applies to any semiconductor structure provided with polysilicon filled deep trenches formed in a silicon substrate coated by a Si3N4 pad layer both in the “array” and “kerf” areas. First, a photoresist mask is formed onto the structure and patterned to expose the deep trenches only in the “array” areas. Deep trenches are then anisotropically dry etched to create recesses having a determined depth. Next, the photoresist mask is removed only in the “array” areas. A step of anisotropic dry etching is now performed to extend said recesses down to the desired depth to create the shallow isolation trenches. The photoresist mask is totally removed. A layer of oxide (STI oxide) is conformally deposited by LPCVD onto the structure to fill said shallow isolation trenches in excess. The structure is planarized to create the STI oxide regions and expose deep trenches in the “kerf” areas.

Abstract: A method for producing a plasma silicon nitride series film with a small heat load having a low hydrogen concentration is provided. The method is for producing a silicon nitride series film on a material to be treated using a plasma CVD apparatus having a reaction chamber evacuated to vacuum. The method comprises the steps of introducing a monosilane gas (SiH4) and a nitrogen gas (N2) as raw material gases into the reaction chamber at prescribed flow rates, and heating the material to be treated to a prescribed temperature. At this time, it is characterized in that the flow rate of the nitrogen gas is at least 100 times the flow rate of the monosilane gas.

Abstract: A ROM is embedded within an array of DRAM cells by changing a single mask in a DRAM fabrication process to selectively short circuit the DRAM capacitor lower electrode to its own wordline to create a read-only “1” or to the wordline of an adjacent cell to create a read only “0”.

Abstract: On an insulating substrate (10), there are formed a first gate electrode (11), a gate insulating film (12), a semiconductor film (13), and an interlayer insulating film (15). Above the interlayer insulating film (15), a TFT is formed having a second gate electrode (17) connected to the first gate electrode (11). Then, a photosensitive resin (70) is formed over the entire surface of the extant layers. Subsequently, first exposure (75) is applied using a first mask (71), and second exposure (76) is then applied using a second mask (72) with a larger amount of light than used for the first exposure. The second mask (72) has an opening at a position corresponding to a source (13s). Thereafter, the photosensitive resin film (70) is developed thereby forming a contact hole (73) and a recess (74).

Abstract: The present invention provides a method for integrating the fabrication of a sensor and a high voltage devices. The N conductive type sensor has a P conductive type doped region in the substrate of the sensor active region to effectively reduce the leakage at edges of the field oxide. Furthermore, there are the P conductive type field and the P conductive type well used as isolations for the sensor and these isolations can prevent blooming. Between these isolations, high voltage devices can be simultaneously formed thereon.

Abstract: Various methods of fabricating circuit devices are provided. In one aspect, a method of fabricating a circuit device on a substrate is provided. The method includes forming a doped silicon structure on the substrate and forming a hemispherical grain silicon film on the silicon structure. The substrate is heated from a first temperature to a second temperature while undergoing exposure to a dopant gas to add a dopant to the hemispherical grain silicon film. The method provides for improved capacitor electrode fabrication via concurrent gas exposure and substrate temperature ramp-up. In this way, dopant gas is introduced before the doped silicon structure transitions from an amorphous state to a polycrystalline state.

Abstract: In a method of manufacturing a glass substrate for a magnetic recording medium for forming a predetermined roughness, a principal surface of the glass substrate is precisely polished by the use of polishing material containing free abrasive grain. Remaining stress distribution for a portion of a polishing trace due to the free abrasive grain is generated on the surface of the glass substrate. A surface process is performed for at least the principal surface of the glass substrate by the use of hydrosilicofluoric acid. A portion having relatively high remaining distortion in the generated remaining stress distribution is decided as an island portion. The glass substrate is heated after precisely polishing before performing the surface process by the use of the hydrosilicofluoric acid.

Abstract: A method for housing sensors in a package and, in particular, housing chemical sensors, flow sensors or optical sensors in a synthetic package. In a first step, the active sensor surface of a semiconductor or IC sensor is provided with a cap forming a hollow space above the active sensor surface and the sensor is connected with contacts and bond wires. In a second method step, the package is formed by molding, in particular injection molding. In a third method step, or simultaneously with the second method step, the hollow space formed above the active sensor surface is opened.

Abstract: A process for forming a vertical double-diffused metal oxide semiconductor (VDMOS) structure comprising a semiconductor substrate, an epitaxial layer on the substrate, and a dielectric gate layer on the epitaxial layer includes implanting a first concentration dopant of a first conductivity type through an aperture defined by edges of a patterned gate conductor layer on the dielectric gate layer so that the first concentration dopant diffuses to form a body region of the VDMOS structure. A mask is formed on the patterned gate conductor layer and on a first portion of the body region for defining apertures exposing second portions of the body region.

Abstract: Multilayer metal materials are selected so that the materials will alloy or intermix under rapid thermal annealing conditions. The individual materials of the multilayers are preferably chosen such that at least one of the materials may be selectively etched with respect to the other material by wet chemical or electrochemical etching. For electroplating applications, the alloyed plating base material will assume some of the etch resistance of the original electrodeposit material such that a selective wet etch of the plating base can be performed without substantial undercutting. Furthermore, the graded composition alloy will exhibit other advantageous physical and chemical properties for electrode formation and use. The alloying or intermixing may be accomplished before or after patterning of the materials, for the instance wherein the materials deposited as blanket layers.

Abstract: A first electrode and a doped oxide layer laterally proximate thereof are provided over a substrate. A silicon nitride layer is formed over both the doped oxide layer and the first electrode to a thickness of no greater than 80 Angstroms over at least the first electrode by low pressure chemical vapor deposition at a pressure of at least 1 Torr, a temperature of less than 700° C. and using feed gases comprising a silicon hydride and ammonia. The substrate with silicon nitride layer is exposed to oxidizing conditions comprising at least 700° C. to form a silicon dioxide layer over the silicon nitride layer, with the thickness of silicon nitride over the doped oxide layer being sufficient to shield oxidizable substrate material beneath the doped oxide layer from oxidizing during the exposing. A second electrode is formed over the silicon dioxide layer and the first electrode. In another implementation, a layer comprising undoped oxide is formed over a doped oxide layer.

Abstract: The silicon real estate consumed by a conventional Schottky diode is reduced in the present invention by forming the Schottky diode through a field oxide isolation region. Etching through the field oxide isolation region requires extra etch time which is provided by conventional etch steps that typically specify a 50-100% overetch during contact formation.

Abstract: A MultiMediaCard fabrication method includes the steps of (1) conductive bracket preparation, (2) bending front legs of the conductive bracket into shape, (3) injection shell, (4) die bond, (5) wire bond, (6) glob top, (7) printing the desired logo and design on the shell of the semi-finished product thus obtained from step (6).

Abstract: An exposure apparatus having an illumination light source and a stage for an exposed object to be mounted thereon, in which at least one of an illumination optical system and a projection optical system includes a plurality of optical articles in each of which a first optically transparent thin layer and a second optically transparent thin layer having a higher refractive index than that of the first optically transparent thin layer are laminated on a surface of a substrate. At least one of the first and second optically transparent thin layers includes a layer of oxides or fluorides and atoms of at least one selected from the group consisting of krypton, xenon and radon, in which the content of the atoms is within a range of from 0.5 atomic ppm to 1 atomic %, inclusive.

Abstract: A method for manufacturing a micromechanical component, in particular, a surface-micromechanical yaw sensor, includes the following steps: providing a substrate having a front side and a back side; forming a micromechanical pattern on the front side; applying a protective layer on the micromechanical pattern on the front side; forming a micromechanical pattern on the back side, a resting on the micromechanical pattern on the front side taking place at least temporarily; removing the protective layer on the front side; and optionally further processing the micromechanical pattern on the front side and/or the micromechanical pattern on the back side.

Abstract: A process for selectively depositing a silicon oxide layer onto silicon substrates of different conductivity types is disclosed. The silicon oxide layer is formed by the ozone decomposition of TEOS at relatively low temperatures and relatively high pressures. Use of the process to produce layers, spacers, memory units, and gates is also disclosed, as well as the structures so produced.

Abstract: A trench-gate semiconductor device, for example a MOSFET or IGBT, of compact geometry is manufactured with self-aligned masking techniques in a simple process with good reproducibility. The source region (13) of the device is formed by introducing dopant (63) into an area of the body region (15) via a mask window (51a), diffusing the dopant to form a surface region (13b) that extends laterally below the mask (51) at a distance (d) beyond the masking edge (51b) of the window (51a), and then etching the body (10) at the window (51a) to form a trench (20) for the trench-gate (11) with a lateral extent (y) that is determined by the etching of the body (10) at the masking edge (51b) of the window (51a). A portion of the surface region (13b) is left to provide the source region (13) adjacent to the trench (20).

Abstract: A method of fabricating a horizontal isolation structure between a deep trench capacitor and a vertical transistor thereon is provided. A deep trench capacitor is in the bottom of a deep trench of a substrate. An insulating layer is formed to partially fill the deep trench and also on the substrate by high-density plasma chemical vapor deposition. The insulating layer on the sidewall of the deep trench and on the substrate is removed to transform the insulating layer in the deep trench to an isolation structure. An alternative approach is to form an insulating layer on the substrate and in the deep trench. Then a CMP is performed to remove the insulating layer on the substrate and an etching back is performed to remove the upper portion of the insulating layer in the deep trench. Then the remained insulating layer in the deep trench is served as an isolation structure between the deep trench capacitor and a vertical transistor thereron.

Abstract: A contact layer is used, for example, as a liner for the fabrication of electrical contacts in contact holes. The contact layer is fabricated in two steps, in a first step a first contact layer is deposited, in which only a small proportion of the particles to be sputtered is ionized. In a second sputtering step, a second contact layer is sputtered, in the course of whose fabrication a larger proportion of the particles to be sputtered is ionized. The procedure ensures that the first contact layer is disposed as a protective layer on the substrate by gentle sputtering before the second contact layer is sputtered.