Abstract: An improved method for forming a buried plate in a bottle-shaped deep trench capacitor. The method includes the steps of: (a) forming a deep trench into a semiconductive substrate; (b) filling the deep trench with a first dielectric material to a first predetermined depth; (c) forming a silicon nitride sidewall spacer in the deep trench above the dielectric layer; (d) removing the first dielectric layer, leaving the portion of the substrate below the sidewall spacer to be exposed; (e) using the sidewall spacer as a mask, causing the exposed portion of the substrate to be oxidized, then removing the oxidized substrate; (f) forming an arsenic-ion-dope conformal layer around the side walls of the deep trench, including the sidewall spacer; (g) heating the substrate to cause the arsenic ions to diffuse into the substrate in the deep trench not covered by the sidewall spacer; and (h) removing the entire arsenic-ion-doped layer.

Abstract: Disclosed is a method for forming a semiconductor device; and, more particularly, to a method for forming a semiconductor device with low parasite capacitance by using an air gap and a self-aligned contact plug formed by a selective epitaxial growing method. A method for forming a semiconductor according to the present invention comprises the steps of: forming word lines over a semiconductor substrate, wherein a plurality of contact areas are formed between the word lines; forming epitaxial layers for contact plugs on the contact areas, thereby forming a resulting structure; forming air gaps on non-contact areas on which the epitaxial layers is not formed, by depositing an interlayer insulation layer on the resulting structure; and patterning the interlayer insulation layer so as to expose the epitaxial layers. Accordingly, the present invention using the air gap as a gap filling materials reduces the parasite capacitance loaded on a bit line and omits an additional gap filling process.

Abstract: The present invention is a method for forming a gate electrode of a transistor in integrated circuits, where the gate electrode is formed by a damascene process. First, a substrate is provided with a gate dielectric layer thereon and a first gate layer is formed on the gate dielectric layer. Next, a first silicon oxide layer is deposited on the first gate layer and an opening through the first silicon oxide layer is formed by an etching process. Then, a first spacer is formed on sidewalls of the first silicon oxide layer in the opening and then the opening is filled with a second gate layer. Following, the first silicon oxide layer and the first spacer are removed to form a gate structure. Next, the first gate layer and the gate dielectric layer around the gate structure are removed. Then, a lightly doped drain, a second spacer, and a source/drain region are formed sequentially in the transistor.

Abstract: A ROM embedded in a multi-layered integrated circuit includes rows of transistor memory cells. For reduced area, each transistor in a row optionally shares a terminal with an adjacent transistor in the row, whereby adjacent transistors share one of a source and a drain. A plurality of contact lines, one each connected to each common terminal, serve as address terminals for cells. A plurality of metal layers are connected to the other of the drain or source terminals by filled vias and include a final metal layer defining a metal pad for each of the other terminals. Filled vias couple selected metal pads to selected signal lines to provide “1” outputs from selected cells and signal lines which are not coupled by filled vias to the metal pads provide “0” outputs from selected cells.

Abstract: A method of manufacturing a self-aligned contact pad for the fabrication of an integrated circuit is disclosed. A plurality of gate structures is formed on the substrate. A first insulating layer is formed over the plurality of gate structures. Then, a second insulating layer is formed over the first insulating layer and filling spaces between the gate structures. Next, a portion of second insulating layer is removed between the gate structures, thereby forming a plurality of contact holes between the gate structures and exposing a portion of the first insulating layer. The exposed portion of the first insulating layer is etched away to form a gate spacer on the sidewalls of the gate structures and exposing surfaces of active regions of the substrate. Finally, the plurality of contact holes are filled with a first conductive layer and the first conductive layer is planarized to form contact pads.

Abstract: A new capacitor and a new method for fabricating the capacitor in an integrated circuit. The method uses fewer steps than those used in prior art processes. In accordance with the invention, trenches of differing depths are formed in a first insulating layer. One of the trenches is etched to expose a conducting layer formed under the insulating layer. Conductive material is deposited in the trenches to form a capacitor. The trenches are formed apart from each other.

Abstract: A silicon nitride film is formed on a substrate so as to cover semiconductor devices. After having formed more than one layer of conducting members and interlayer dielectric portion, such as silicon oxide interlayer films on the silicon nitride film, an opening is formed in said interlayer dielectric portion so as to reach the silicon nitride film. The substrate with thus defined opening is etched in an etching solution containing hydrogen fluoride acid therein to remove away the silicon oxide interlayer portion. As the silicon oxide interlayer portion is etched in the solution, this forms electrical interconnection that are not surrounded with any oxides. As the silicon nitride film works as an etching stopper layer in this etching above, the semiconductor devices are protected against the etching process.

Abstract: A method is provided for inspecting solder-bumped joints of a semiconductor package assembly comprising a packaged semiconductor device and a substrate, such as a circuit board. Embodiments include immersing the package assembly in a dye solution, such as red tracer dye, then placing the immersed package assembly under a vacuum such that, when cracks exist between the solder bumps and substrate bonding pads, or between the solder bumps and the semiconductor device bonding pads, the dye solution flows into the cracks. The package assembly is removed from the vacuum and the dye solution, dried, and the semiconductor device and the substrate manually separated. Thereafter, the substrate bonding pads and the semiconductor device bonding pads are inspected, as with an optical microscope, for residual dye, indicating cracked solder joints. Thus, cracked solder joints, and the full extent of the cracks, are clearly indicated by the presence of dye on the bonding pads after the inventive procedure is performed.

Abstract: A polishing cloth used for a chemical mechanical polishing comprises a base body holding a slurry on the surface and serving to mechanically polish the surface of a target object to be polished. Fine particles soluble in a solvent are dispersed in the base body.

Abstract: A method of forming a line of FLASH memory cells includes forming a first line of floating gates over a crystalline silicon semiconductor substrate. An alternating series of SiO2 isolation regions and active areas are provided in the semiconductor substrate in a second line adjacent and along at least a portion of the first line of floating gates. The series of active areas define discrete transistor source areas. A masking layer is formed over the floating gates, the regions and the areas. A third line mask opening is formed in the masking layer over at least a portion of the second line. Anisotropic etching is conducted of the SiO2 isolation regions exposed through the third line mask opening substantially selectively relative to crystalline silicon exposed through the third line mask opening using a gas chemistry comprising a combination of at least one non-hydrogen containing fluorocarbon having at least three carbon atoms and at least one hydrogen containing fluorocarbon.

Abstract: Two contradictory problems of the reduction in the thickness of semiconductor chips or package parts including the semiconductor chips and the improvement in mechanical strength are solved. A semiconductor wafer where semiconductor elements are formed on a first surface thereof or semiconductor chips formed by dicing the semiconductor wafer are reduced in thickness by grinding the second surface opposite to the first surface, and grinding scratches formed by the grinding are removed to smooth the second surface. Since dicing scratches are formed on side surfaces of the semiconductor chips by dicing, the side surfaces are etched together with the second surface to remove the dicing scratches as well as the grinding scratches, thereby smoothing the second surface and the side surfaces.

Abstract: The invention is a two-step dual-chemistry process for etching through a selected portion of an insulating oxide layer of a substrate to create a self-aligned contact opening without damaging underlying field oxide regions. The first etching step uses essentially a CxFy (x>1)-type chemistry that etches only partially through the oxide layer, since it has very good selectivity to the silicon nitride cap of the gate stacks but a poor selectivity to the field oxide regions. The second etching step employs a second chemistry comprising an H-containing fluorocarbon chemistry. The second chemistry has a good selectivity to the field oxide regions and, at the same time, is able to finish etching the opening.

Abstract: A flip-chip-type device is formed from a plurality of flip-chip semiconductor device units integrated together on a common substrate having a Group III nitride compound semiconductor layer. Each of the flip-chip semiconductor device units includes a positive electrode and a negative electrode. A curable sealing resin is laminated on a surface of the common substrate on which electrodes are formed and cured. Thereafter, the common substrate and the cured sealing resin are divided into a plurality of individual sealed flip-chip semiconductor devices. Because the positive and negative electrodes are formed on the same side of the Group III nitride compound layer, the sealing resin need only be laminated and cured on one side of the Group III nitride compound layer, i.e., on the side on which the electrodes are formed.

Abstract: In producing a thin film transistor used for such devices as a large-sized liquid crystal display panel with a high pixel density, a leftover of an insulating film caused by insufficient etching and a loss of a semiconductor layer caused by overetching are prevented, and a reliable electrical contact between the source and drain electrodes and the semiconductor layer is achieved. These are achieved by (a) forming a contact hole region of a silicon film so that the region has a larger thickness, for example, by making the film to have a plurality of layers, and (b) providing a silicide layer between an electrode metal and the semiconductor layer.

Abstract: A copper layer is formed in wiring grooves formed in a semiconductor substrate and also on the semiconductor substrate. The semiconductor substrate is brought into contact with a culture solution containing bacteria whose size is larger than the width of the wiring grooves. The copper layer on the semiconductor substrate is removed by the bacteria comprising autotroph, but the copper layer in the wiring grooves is not removed because the bacteria cannot enter the wiring grooves.

Abstract: A method for manufacturing a semiconductor device includes the steps of (1) forming a pad oxide film of 5 nm or more on a circuit forming surface of a semiconductor substrate; (2) forming an oxidation inhibition film on the pad oxide film; (3) forming grooves of a given depth with the oxidation inhibition film as a mask; (4) receding the pad oxide film; (5) oxidizing the grooves formed on the semiconductor substrate in the range of 0<C≦0.88t-924 in which the oxidizing atmosphere is dry oxidation (H2/O2≈0), the oxygen partial pressure in the air corresponding to the oxygen partial pressure ratio is C %, and the oxidizing temperature is t (° C.

Abstract: The present application discloses a method of forming and operating a metal-to-metal antifuse with an amorphous carbon dielectric which provides a very high resistance off state and can be programmed at voltages compatible with deep submicron devices. Furthermore, the programmed filament achieves low resistance with low programming current while maintaining a high level of stability.

Abstract: A first electrode and a doped oxide layer laterally proximate thereof are provided over a substrate. A silicon nitride layer is formed over both the doped oxide layer and the first electrode to a thickness of no greater than 80 Angstroms over at least the first electrode by low pressure chemical vapor deposition at a pressure of at least 1 Torr, a temperature of less than 700° C. and using feed gases comprising a silicon hydride and ammonia. The substrate with silicon nitride layer is exposed to oxidizing conditions comprising at least 700° C. to form a silicon dioxide layer over the silicon nitride layer, with the thickness of silicon nitride over the doped oxide layer being sufficient to shield oxidizable substrate material beneath the doped oxide layer from oxidizing during the exposing. A second electrode is formed over the silicon dioxide layer and the first electrode. In another implementation, a layer comprising undoped oxide is formed over a doped oxide layer.

Abstract: A Schottky diode, and a method of making the same, which is fabricated on InP material and employs a Schottky layer including InxAl1−xAS with x>0.6, or else including a chirped graded superlattice in which successive periods of the superlattice contain progressively less GaInAs and progressively more AlInAs, the increase in AlInAs being terminated before the proportion of AlInAs within the last period (adjacent the anode metal) exceeds 80%.

Abstract: A method of forming a capacitor with a self-align structure on a substrate, the substrate including a word line and an active region, the method including the steps of forming a first dielectric layer on the active region and the word line with a planar top surface, creating a contact hole in the first dielectric layer with the self-align structure to expose portions of the active region and the word line, forming a conductive layer on the bottom of the contact hole, forming a polysilicon spacer on the sidewall of the contact hole, forming a dielectric spacer on the sidewall of the polysilicon spacer, filling the contact hole with a polysilicon bar, creating three sub-contact holes by etching back the polysilicon spacer and the polysilicon bar with part of the polysilicon spacer and the polysilicon bar remaining on the bottom, forming a hemispherical grain (HSG) layer on the surface of the sub-contact holes, depositing a second dielectric layer on the hemispherical grain, and forming a top electrode on the se