Abstract: A method for dividing a semiconductor wafer which is covered by an opaque resin in a dicing process includes forming marks on the semiconductor wafer, wherein the marks are distinguished from electrodes which are formed on the semiconductor wafer. According to the method, in a dicing process, separating semiconductor chips from the semiconductor wafer can be precisely achieved.

Abstract: An array of P-channel memory cells is separated into independently programmable memory segments by creating multiple, electrically isolated N-wells upon which the memory segments are fabricated. The methods for creating the multiple, electrically isolated N-wells include p-n junction isolation and dielectric isolation.

Abstract: A method for eliminating source/drain shorting generated during the highly-doped source/drain implant steps in a standard STI process is provided. This is achieved by reducing the RTA temperature to be less than 1000° C. so as to minimize enhanced doping diffusion. Further, the energy level for the highly-doped source/drain implant steps is increased so to compensate for poly depletion in the gate electrodes.

Abstract: A semiconductor package having: a chip-sized wiring board that has a predetermined wiring pattern; a semiconductor chip that is mounted on the wiring board and is electrically connected to the wiring pattern; sealing resin that seals at least the connection part of the wiring board and the semiconductor chip; an array of solder balls for external circuit connection that are connected through an opening in the sealing resin to a land of the wiring pattern; and a protective member that is disposed along at least two sides of the surface where the array of solder balls are provided.

Abstract: A method of fabricating a tunneling photodiode is presented comprised of the following steps: forming a p-well in an n-type substrate, forming a thin insulating layer over the surface of the p-type material, and then forming a thin n-type layer over the insulating layer. Preferably, the n and p type semiconductor material could be silicon and the insulating layer could be between about 30 to 40 angstroms of gate quality silicon dioxide. In other embodiments of the invention the materials of either electrode are either n or p-type semiconductors or metals.

Abstract: A method for manufacturing a semiconductor device includes the steps of (1) forming a pad oxide film of 5 nm or more on a circuit forming surface of a semiconductor substrate; (2) forming an oxidation inhibition film on the pad oxide film; (3) forming grooves of a given depth with the oxidation inhibition film as a mask; (4) receding the pad oxide film; (5) oxidizing the grooves formed on the semiconductor substrate in the range of 0<C≦0.88t−924 in which the oxidizing atmosphere is dry oxidation (H2/O2≈0), the oxygen partial pressure in the air corresponding to the oxygen partial pressure ratio is C %, and the oxidizing temperature is t (° C.

Abstract: A method of making an integrated circuit includes forming a plurality of copper interconnect layers adjacent a semiconductor substrate. The plurality of copper interconnect layers are then annealed, in a deuterium ambient, prior to chemical mechanical polishing of such layers. The microstructure of each of the copper interconnect layers is thereby stabilized.

Abstract: A method for forming borderless contact is disclosed. The method includes providing a substrate with active areas and a trench isolation region in which the active areas are silcide. Then, the substrate is nitridized such that a titanium nitride layer is formed on the active areas and a silicon oxynitride is formed on the trench isolation region. A dielectric layer is deposited on the substrate and an opening is etched in the dielectric layer in which the opening overlies both a portion of the trench isolation region and a portion of the active area.

Abstract: A method for forming ultra shallow junctions in a semiconductor wafer with reduced junction leakage arising from a silicidation process due to grain boundary induced stress induced junction spiking amorphizes the metal layer prior to annealing during silicidation. After the gate and source/drain junctions are formed in a semiconductor device, dopant or non-dopant material is implanted into the anamorphous metal layer that has been previously deposited over the gate and source/drain junctions. The ion implantation is performed at an energy level sufficient to amorphize the metal (e.g. cobalt), and substantially eliminate grain boundaries in the metal and release grain boundary induced stress. This prevents grain boundary stress induced diffusion of the metal during the first phase of the silicidation process, where the metal is the diffusing species. The silicide regions that are formed during subsequent annealing steps therefore do not exhibit junction spikes.

Abstract: The present invention provides a method of forming trench capacitor with a sacrificial silicon nitride. A deep trench structure is formed in a substrate. A TEOS oxide layer is formed on the substrate and filled in said trench region, etched to a first level subsequently, wherein a portion of the TEOS oxide layer is remained in the trench region and a portion of the substrate exposed to form a trench sidewall. A thermally oxidation process is performed to form a collar oxide on the exposed substrate. A silicon nitride sidewall is formed on the collar oxide, then removing the residual TEOS oxide layer by wet etching. The trench region is then etched using the silicon nitride sidewall as a barrier to form a bottle shape trench region for increasing the surface of the trench region. A bottom cell plate is formed in the fresh trench region. The silicon nitride sidewall is removed.

Abstract: A process for manufacturing a semiconductor circuit. The process comprises creating a plurality of adjacent conductive lines having a solid fill between the conductive lines; creating one or more layers above the lines and the fill; creating one or more pathways to the fill through the layers; and converting the fill to a gas that escapes through the pathways, leaving an air void between adjacent lines. To protect the lines from oxidation during processing, a related process for encapsulating conductive lines in one or more adhesion-promotion barrier layers may be performed. The encapsulation process may also be practiced in conjunction with other semiconductor manufacturing processes. The processes result in a multi-layer semiconductor circuit comprising conductive lines, wherein the lines have air as a dielectric between them, are encapsulated by an adhesion-promotion barrier layer, or both.

Abstract: A trench (21) is formed in a silicon substrate (1) on which an underlying oxide film (2) and a silicon nitride film (3) are formed. Then, a silicon oxide (11) is deposited by an HDP-CVD method to fill the trench (21) with the oxide. Further, a resist (41) including a second resist portion (42), and a resist (43) are formed. The silicon oxide film (11) that is not covered with the resists (41) and (43), is removed by dry etching. Etch selectivity of the silicon oxide film (11) to the stopper film (3) is not less than a value (2(c−a)/d) obtained by dividing twice a value (c−a) which is obtained by subtracting an alignment margin (a) from the maximum film thickness (c) of the silicon oxide film (11), by the film thickness (d) of the stopper film (3). The resists (41) and (43) are then removed, and the residual silicon oxide film (11B, 11DC, 11DE, 11FE) is polished and removed by the CMP method. This forms a trench type element isolation with no depression at its edge portion.

Abstract: A method for making a photovoltaic device comprises the steps of depositing a hydrogen-containing n-type silicon semiconductive layer, a hydrogen-containing i-type silicon semiconductive layer, and a hydrogen-containing p-type silicon semiconductive layer, in that order, on a supporting substrate. In the step of depositing the hydrogen-containing n-type silicon semiconductive layer, an n-type amorphous semiconductive layer and then an n-type microcrystalline semiconductive layer are deposited to constitute the hydrogen-containing n-type silicon semiconductive layer. The hydrogen-containing n-type silicon semiconductive layer is annealed. Further, an i-type microcrystalline silicon semiconductive layer as the hydrogen-containing i-type silicon semiconductive layer is formed on the annealed hydrogen-containing n-type silicon semiconductive layer.

Abstract: In a method of manufacturing a TFT using a crystalline silicon film in which defects are compensated by a thermal oxidation step, the roughness of a thermal oxidation film formed by thermal oxidation is made small. In the method, first, an amorphous silicon film to which an impurity for suppressing crystallization, such as nitrogen, oxygen, or carbon, is formed on a crystalline silicon film used as an active layer. Since crystallization of this amorphous silicon film is suppressed, it can be thermally oxidized in the state of an amorphous or microcrystalline, and the thermal oxidation film with small roughness can be obtained. By using this thermal oxidation step, it is possible to suppresses generation of a gate leak, to suppresses fluctuation of TFT characteristics in the same substrate to the minimum, and to manufacture a semiconductor device capable of operating at high speed.

Abstract: A method of manufacturing copper-indium-gallium-diselenide (CuInxGa1-xSe2 or just CIGS) photovoltaic devices using elemental selenium and without requiring complex codeposition or requiring the use of toxic H2Se gas. A precursor taking one of several forms is deposited onto a substrate having a back contact. A first precursor includes copper, gallium, and indium, the latter of which is deposited in the presence of a selenium flux, all deposited in that order. The second precursor includes indium deposited in the presence of a selenium flux, copper, and gallium, deposited in that order. Next, the precursor is selenized using one of two techniques: an indium-gallium removal technique and a copper-top technique. In both techniques, the precursor is heated to and held at a first selenization temperature, most preferably 450° C., and then heated to and held at a second selenization temperature, most preferably 550° C.

Abstract: This application relates to a process to suppress the impurity diffusion through gate oxide on silicided amorphous-Si gate structures that utilize the silicide layers as the implantation barrier to minimize the impurity diffusion by reducing the projectile range and implant-induced defects, resulting in smaller flat-band voltage(VFB) shift and better characteristics of the breakdown field(Ebd) and charge to breakdown(Qbd). In addition, the amorphous-Si underlying layer is simultaneously kept during the formation of a low-temperature self-aligned silicide (SAD) process to further retard the impurity diffusion. Hence, the usage of such bilayered silicide/amorphous-Si films could effectively retard the impurity diffusion, by combining both effects of the amorphous-Si layer and the silicide process or inducing other undesirable effects such as the increase of gate sheet resistance.

Abstract: A process for manufacturing a MOS transistor and especially a MOS transistor used for non-volatile memory cells is presented. At the start of the manufacturing, a semiconductor substrate having a first type of conductivity is covered by a gate oxide layer. A gate electrode is formed over the gate oxide layer, which is a stacked gate when the MOS transistor is used in a non-volatile memory. Covering the gate electrode is a covering oxide that is formed over the gate oxide layer, the gate electrode, and around the gate electrode. Next, a dopant of a second type of conductivity is implanted to provide implant regions adjacent to the gate electrode. Subjecting the semiconductor to thermal treatments allows the implanted regions to diffuse into the semiconductor substrate under the gate electrode and form a gradual junction drain and source region of the MOS transistor.

Abstract: The present invention proposes a method for fabricating high-density and high-speed NAND-type mask read-only memories. This method constructs the doped sources and drains by dopant diffusion into the silicon substrate to form ultra-shallow junction, and therefore minimizes the punch-through issue. First, a stacked thin oxide, doped silicon and silicon nitride layer is deposited on the semiconductor substrate and then bit line regions is defined. Gate oxide film is formed between the bit line regions and the dopants in the silicon layer are driven into the substrate to form shallow junctions for source and drain regions. A doped polysilicon layer is deposited on the substrate and a chemical mechanical polishing process is carried out with the silicon nitride as the stopping layer. A coding implantation is performed and a conductive layer is defined on the polysilicon layer to be the word lines.

Abstract: The invention provides a floating gate memory cell, where the floating gate comprises a first lateral end region and a second lateral end region. A middle region is positioned towards a middle of the floating gate with respect to the first lateral end region and the second lateral end region. The thickness of the floating gate decreases continuously from at least one of the first or second lateral end regions to the middle region. This invention also provides for a method of forming a contoured floating gate for use in a floating gate memory cell.

Abstract: An electronic module having enhanced adhesion at the chip passivation and underfill interface is disclosed. The surface of the chip passivation is chemically modified to a sufficient depth such that the cured passivation is more reactive. The modified surface is treated with a polyamine preferably having a cyclic amine group extending from a preferably aliphatic backbone. During reflow of the solder joints of the electronic module by heating, the modified passivation reacts with the polyamine at the amine functionality. Following underfill of the electronic module with a polymeric material, preferably an epoxy resin, the polyamine on the surface of the passivation reacts with the underfill material during curing of the underfill material. The resulting electronic module is more robust since the amine acts as a chemical anchoring site for both the modified passivation and the underfill material.