Abstract: A method for forming a retrograde impurity profile in a semiconducting substrate is provided. The method comprises forming a sacrificial layer having a thickness in the range of about 10 Å to about 150 Å on the surface of a semiconducting substrate. Thereafter, an ion implantation process is performed wherein dopant impurity ions are directed through the sacrificial layer and into the semiconducting substrate under conditions effective to form a retrograde impurity profile in the semiconducting substrate.

Abstract: A method and apparatus for forming a layer of underfill encapsulant on an integrated circuit located on a wafer are described. As a flip chip, the integrated circuit has electrically conductive pads, most of which have a solder ball attached thereto. Most of the solder balls have been flattened in order to provide an enlarged solder wetting area. A layer of underfill encapsulant is injected onto the integrated circuit under pressure to form a layer of underfill encapsulant that is then pre-cured. The integrated circuit is mounted to a substrate and the substrate and the integrated circuit are electrically coupled by a solder reflow operation which also finally cures the underfill encapsulant.

Abstract: A method for crystallizing an amorphous silicon layer and for fabricating a thin film transistor. An amorphous silicon layer is formed on a substrate, and patterned to form an active layer by etching the amorphous silicon layer using photolithography. The amorphous silicon layer is crystallized using sequential lateral solidification to form a crystallized active layer having a smooth surface. A smooth surface is obtained by the crystallization process without a subsequent smoothing step by canceling an increased volume of silicon during crystallization for an increased surface of the active silicon layer. The crystallized silicon layer is used to form a thin film transistor by forming a gate insulating layer and a gate electrode on the crystallized active layer, and forming a source and a drain region by doping the crystallized active layer with impurities in use of the gate electrode as a mask.

Abstract: A plastic package assembly method suitable for ferroelectric-based integrated circuits includes a strict thermal budget that reduces the time at temperature for four key processing steps: die attach cures, die coat cures, molding cures, and marking cures. The plastic package assembly method uses low temperature mold and die coat materials, as well as low temperature curable inks or laser marking in order to minimize degradation of electrical performance, thus improving yields and reliability. The assembly method uses a snap cure die attach step, a die coat followed by a room temperature cure, and formation of the plastic package with room temperature curable molding compounds not requiring a post mold cure. Front and back marking of the plastic package is accomplished using either an infrared or ultraviolet curable ink followed by minimum cure time at elevated temperature, or by using laser marking.

Abstract: A method of forming a semiconductor structure may include forming a semiconductor substrate having an array region and a support region, forming a semiconductor substrate and a gate stack over the support region of the substrate and applying a critical mask over the support region and the array region. The critical mask may have a first opening at an area corresponding to the array region and a second opening at an area corresponding to the support region. Contact holes may be formed in a glass layer at areas corresponding to the first and second opening. After removing the critical mask, a first blockout mask may be applied over the array region and a first conductive type dopant may be added to exposed polysilicon corresponding to openings of the blockout mask or gate contacts may be formed.

Abstract: A method for removing impurities and deposits formed in a contact hole of a semiconductor device. The method comprises the step of bathing the semiconductor device in a solution having concentrations of between about 25 to 35 weight percent of Isopropyl Alcohol (IPA), 2 to 4 weight percent of H2O2, 0.05 to 0.25 weight percent of HF, and the remaining percent of deionized water. Such bathing is preferably carried out with the solution maintained at a constant temperature of between about 20 to 25° C. for about 1 to 5 minutes.

Abstract: A method is disclosed to form a plurality of oxides of different thicknesses with one step oxidation. In a first embodiment, a substrate is provided having a high-voltage cell area and a peripheral low-voltage logic area separated by a trench isolation region. The substrate is first nitrided. Then the nitride layer over the high-voltage area is removed, and the substrate is wet cleaned with HF solution. The substrate surface is next oxidized to form a tunnel oxide of desired thickness over the high-voltage. In a second embodiment, a sacrificial oxide is used over the substrate for patterning the high voltage cell area and the low-voltage logic area. The sacrificial oxide is removed from the low-voltage area and the substrate is nitrided after cleaning with a solution not containing HF, thus forming a nitride layer over the low-voltage area. Then, the sacrificial oxide is removed from the high-voltage area with an HF dip, and tunnel oxide of desired thickness is formed over the same area.

Abstract: In an IGFET device having at least one source/drain region with a lightly-doped sub-region proximate a channel region, the source/drain regions are formed by first implanting ions with parameters to form lightly-doped source/drain regions. A high density plasma deposition provides at least one spacer having preselected characteristics. As a result of the spacer characteristics, an ion implantation with parameters to form normally-doped source/drain regions is shadowed by the spacer. A portion of the source/drain region shadowed by the spacer results in a lightly-doped source/drain sub-region proximate the channel region. According to a second embodiment of the invention, the ion implantation resulting in the lightly-doped source/drain regions is eliminated. Instead, the spacer(s) formed by the high density plasma deposition and subsequent etching process only partially shadows the ion implantation that would otherwise result in normal doping of the source/drain regions.

Abstract: A method of manufacturing a semiconductor device having a silicon substrate containing an impurity diffusion layer is disclosed, that comprises the steps of doping impurities to the silicon substrate through a silicon oxide film with a thickness of 2.5 nm or less at an accelerating voltage of 3 keV or less, the silicon oxide film being formed on the silicon substrate and annealing the silicon substrate with the oxide film left.

Abstract: To obtain a small contact-less memory device, a memory device includes a semiconductor chip having a first surface and a second surface located at a level lower than that of the first surface, a memory cell array formed on the second surface, a peripheral circuit, for operating the memory cell array, formed on the first surface, and a connecting portion, for electrically connecting the memory cell array to the peripheral circuit, formed on the first surface.

Abstract: A method for depositing a rough polysilicon film on a substrate is disclosed. The method includes introducing the reactant gases argon and silane into a deposition chamber and enabling and disabling a plasma at various times during the deposition process.

Abstract: The present invention provides a process for fabricating merged integrated circuits on a semiconductor wafer substrate. The process comprises forming a gate oxide on the semiconductor wafer substrate, forming a first transistor having a first gate on the gate oxide, and forming a second transistor having a second gate on the same gate oxide. The first transistor is optimized to a first operating voltage by varying a physical property of the first gate, varying a first tub doping profile, or varying a first source/drain doping profile. The second transistor is optimized to a second operating voltage by varying a physical property of the second gate, varying a second tub doping profile, or varying a second source/drain doping profile of the second transistor. These physical characteristics may be changed in any combination or singly to achieve the determined optimization of the operating voltage of any given transistor.

Abstract: A channel write/erase flash memory cell structure together with its method of manufacture and mode of operation. The flash memory cell structure is formed by implanting P-type ions into a substrate to form a shallow-doped region, and then implanting N-type ions to form the drain terminal of the flash memory cell. Next, a deep-doped region that acts as a P-well is formed underneath the drain terminal. Method of manufacturing the channel write/erase memory cell and its mode of operation is also discussed.

Abstract: A method for forming a thin-film resistor, which is composed of silicon, carbon, and chromium, is disclosed. The resistivity of the thin-film resistor, and therefore the resistance and temperature coefficient of resistance (TCR) of the resistor, are tailored to have specific values by varying the elemental composition of the silicon, carbon, and chromium used to form the resistor.

Abstract: A first electrode and a doped oxide layer laterally proximate thereof are provided over a substrate. A silicon nitride layer is formed over both the doped oxide layer and the first electrode to a thickness of no greater than 80 Angstroms over at least the first electrode by low pressure chemical vapor deposition at a pressure of at least 1 Torr, a temperature of less than 700° C. and using feed gases comprising a silicon hydride and ammonia. The substrate with silicon nitride layer is exposed to oxidizing conditions comprising at least 700° C. to form a silicon dioxide layer over the silicon nitride layer, with the thickness of silicon nitride over the doped oxide layer being sufficient to shield oxidizable substrate material beneath the doped oxide layer from oxidizing during the exposing. A second electrode is formed over the silicon dioxide layer and the first electrode. In another implementation, a layer comprising undoped oxide is formed over a doped oxide layer.

Abstract: In a fabricating method of a semiconductor storage device, a ferroelectric film is formed on a lower electrode, and crystallized. Thereafter, a heat treatment is performed in an atmosphere of hydrogen or a mixture of hydrogen and an inert gas to vanish a defect at the interface between the gate insulating film of a MOS transistor and a silicon substrate. Next, an upper electrode is formed on the ferroelectric film.

Abstract: A ferroelectric thin film includes: a bismuth oxide polycrystal thin film constituting a buffer layer, and a bismuth-based layered compound thin film represented by the formula: Bi2Am-1BmO3m+3 wherein A is an atom selected from the group consisting of Na, K, Pb, Ca, Sr, Ba and Bi; B is an atom selected from the group consisting of Fe, Ti, Nb, Ta, W and Mo; and m is an integer of 1 or more. The bismuth oxide polycrystal thin film and the bismuth-based layered compound thin film are formed into a single-phase.

Abstract: A method of anodizing a lightly doped wafer wherein there is provided a lightly p-typed doped silicon wafer having a frontside and a backside. A p-type region is formed on the backside doped sufficiently to avoid inversion to n-type when a later applied current density of predetermined maximum value is applied to the backside. The wafer is placed in the electrolyte of a chamber having an electrolyte and having a pair of electrodes, preferably platinum, on opposite sides of the wafer and in the electrolyte. The current of predetermined value is passed between the electrodes and through the wafer, the current being sufficient to cause pores to form on the frontside of the wafer. The chamber preferably has first and second regions, one of the electrodes being disposed in one of the regions and the other electrode being disposed in the other regions with the wafer hermetically sealing the first region from the second region.

Abstract: An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures having reduced polysilicon gate length, reduced parasitic capacitance and gradual doping profiles is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer over the gate oxide layer; forming a first mask layer over the polysilicon layer; patterning and etching the first mask layer to form a first gate mask; anisotropically etching the polysilicon layer to form a polysilicon gate, wherein the polysilicon gate comprises sidewalls with re-entrant profiles, and implanting the semiconductor substrate with a dopant to penetrate portions of the sidewalls to form one or more graded shallow junctions with gradual doping profiles. The gradual doping profiles reduce parasitic capacitance and minimize hot carrier injections.

Abstract: This invention comprises a new technique to realize a dual material gate MOSFET. The inventive technique is base upon an asymmetric oxide spacer formation and a self-aligned silicide formation. The asymmetric oxide spacer on the sidewall of the drain side of the gate is formed by selectively etching the spacer on the source side. The etch selectivity is realized by nitrogen implantation into an oxide spacer on the source side, by utilizing preferably an angled ion implantation technique. An HF solution has been experimentally demonstrated to provide an etch rate of the nitrogen implanted oxide that is much faster than the oxide without the nitrogen implantation.