Abstract: A package substrate comprising a thin film redistribution layer (RDL) with a plurality of metal pillar configured on chip side is disclosed to thin the thickness of an IC package before mounting to a circuit board. The height of metal pillar keeps a proper distance between the IC chip and the package substrate so that an underfill material can be filled in between to ensure the reliability of the IC package.

Abstract: An integrated circuit device includes a first pad group connected to a first memory pad group arranged along a first chip side of a chip of an image memory stacked on the integrated circuit device, a second pad group connected to a second memory pad group arranged along a third chip side, a control section which controls display of an electro-optical device, and a third pad group from which a data signal and a control signal for display control. The first pad group is arranged along a first side of the integrated circuit device, wherein the second pad group is arranged along a third side facing the first side, and wherein the third pad group is arranged along a second side which intersects with the first side and the third side.

Abstract: A method of making an assembly includes the steps of applying metallic nanoparticles to exposed surfaces of conductive elements of either of or both of a first component and a second component, juxtaposing the conductive elements of the first component with the conductive elements of the second component with the metallic nanoparticles disposed therebetween, and elevating a temperature at least at interfaces of the juxtaposed conductive elements to a joining temperature at which the metallic nanoparticles cause metallurgical joints to form between the juxtaposed conductive elements. The conductive elements of either of or both of the first component and the second component can include substantially rigid posts having top surfaces projecting a height above the surface of the respective component and edge surfaces extending at substantial angles away from the top surfaces thereof.

Abstract: A phosphor and a light emitting device are provided. The phosphor comprises a composition having a formula of (BaaSr1-a)2-zSi5ObNn:EuZ, 0.03<a<0.75, 0<b<1, 7<n<9, and 0.03<z<0.3.

Abstract: There is provided a semiconductor light emitting device comprising a semiconductor stack having first and second main surfaces opposing each other, and comprising first and second conductivity-type semiconductor layers respectively defining the first and second main surfaces, and an active layer interposed between the first and second conductivity-type semiconductor layers; a plurality of contact holes penetrating the second conductivity-type semiconductor layer and the active layer, and one region of the first conductivity-type semiconductor layer; a first electrode layer disposed on the second main surface of the semiconductor stack, the first electrode layer extending and being connected to the one region of the first conductivity-type semiconductor layer through the contact holes; a second electrode layer disposed between the semiconductor stack and the first electrode layer and connected to the second conductivity-type semiconductor layer; and first and second interconnected bumps.

Abstract: A semiconductor device comprises an n+ type SiC semiconductor substrate, an n type low concentration drift layer of an SiC semiconductor on the substrate, p type channel regions selectively arranged in the drift layer with a specified distance between the channel regions, an n type source region selectively arranged in the channel region, a source electrode in common contact with the source region and the channel region, and a gate electrode disposed over the drift layer between two channel regions, and over a part of the channel region positioned between the drift layer and the source region intercalating a gate oxide film therebetween. The drift layer has a low concentration of at most 70% of the concentration that is required to exhibit a specified withstand voltage at a minimum ON resistance.

Abstract: There is provided a light emitting device in which low power consumption can be realized even in the case of a large screen. The surface of a source signal line or a power supply line in a pixel portion is plated to reduce a resistance of a wiring. The source signal line in the pixel portion is manufactured by a step different from a source signal line in a driver circuit portion. The power supply line in the pixel portion is manufactured by a step different from a power supply line led on a substrate. A terminal is similarly plated to made the resistance reduction. It is desirable that a wiring before plating is made of the same material as a gate electrode and the surface of the wiring is plated to form the source signal line or the power supply line.

Abstract: Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension.

Abstract: In a semiconductor device 100 according to the present invention in which a semiconductor member 120 is stacked on a substrate 110, the semiconductor member 120 and the substrate 110 are bonded together by means of a semiconductor device bonding material 130 of which main component is zinc. Further, a coating layer to prevent diffusion of the semiconductor device bonding material 130 is provided on at least one of the surface of the substrate 110 and the surface of the semiconductor member 120. In addition, the coating layer 140 is configured such that a barrier layer 141 composed of nitride, carbide, or carbonitride and a protective layer 142 composed of a noble metal are stacked. Further, the nitride, the carbide, or the carbonitride composing the barrier layer 141 is selected so as to have free energy smaller than that of a material composing an insulating layer 111 provided in the substrate 110.

Abstract: A lead frame with a radiator plate on which a semiconductor chip 50 is to be mounted is provided with a radiator plate 30, and a lower surface side lead frame 40 including an upper surface 41 and a lower surface 42. The lower surface side lead frame 40 overlaps and fixes the radiator plate 30 with the lower surface 42 making contact with the radiator plate 30. A through hole 43 piercing the lower surface side lead frame 40 from the upper surface 41 to the lower surface 42 is formed at a position where the lower surface side lead frame 40 overlaps the radiator plate 30, and an opening area of the through hole 43 at the lower surface 42 is larger than an opening area of the through hole 43 at the upper surface 41.

Abstract: Bondability and heat conductivity of a bonded body in which some of metal, ceramic, or semiconductor are bonded to each other are improved. In the bonded body in which a first member and a second member each comprise one of metal, ceramic, or semiconductor are bonded to each other, the second member is bonded to the first member by way of an adhesive member disposed to the surface of the first member, and the adhesive member contains a V2O5-containing glass and metal particles.

Abstract: Various aspects of the present disclosure provide a semiconductor device and a method for manufacturing thereof, which can facilitate stacking of semiconductor die while saving manufacturing cost. In an example embodiment, the semiconductor device may comprise a first semiconductor die, a second semiconductor die bonded to a top surface of the first semiconductor die, and a redistribution layer electrically connecting the first semiconductor die to the second semiconductor die, wherein the redistribution layer is formed to extend along surrounding side portions of the second semiconductor die.

Abstract: Disclosed is a light-emitting element with a good carrier balance and manufacturing method thereof which does not require the formation of the heterostructure. The light-emitting element includes an organic compound film containing a first organic compound as the main component (base material) between an anode and a cathode, wherein the organic compound film is provided in contact with the anode and with the cathode. The first organic compound further includes a light-emitting region to which a light-emitting substance is added and includes a hole-transport region to which a hole-trapping substance is added and/or an electron-transport region to which an electron-trapping substance is added. The hole-transport region is located between the light-emitting region and the anode, and the electron-transport region is located between the light-emitting region and the cathode.

Abstract: A display device includes a main body, a support stand, and a display portion. The display portion includes a pixel having a TFT and a capacitor. The capacitor includes a capacitor electrode on an insulating surface, an insulating film on the capacitor electrode, and a pixel electrode of the TFT on the insulating film.

Abstract: A package structure includes a flexible-rigid PCB and a chip. The flexible PCB includes a flexible PCB, a glue piece and an outer trace layer. The flexible PCB includes two bending portions and a fixing portion connected between the two bending portions, and includes an insulating layer and an inner trace layer formed on the insulating layer. The glue piece is adhered to the fixing portion. The outer trace layer is adhered to the glue piece and includes conductive pads. The fixing portion, the glue piece and the outer trace layer form a rigid portion, the bending portions form flexible portions. The chip is packaged on the rigid portion and includes electrode pads electrically connected to the conductive pads.

Abstract: A semiconductor package includes a single semiconductor die and an electrically and thermally conductive base. The single semiconductor die includes a semiconductor body having opposing first and second surfaces and insulated sides between the first and second surfaces. The single semiconductor die further includes a first electrode at the first surface and a second electrode at the second surface. The single semiconductor die has a defined thickness measured between the first and second surfaces, a defined width measured along one of the insulated sides, and a defined length measured along another one of the insulated sides. The base is attached to the second electrode at the second surface of the single semiconductor die and has the same length and width as the single semiconductor die.

Abstract: Techniques and structure are disclosed for providing a MIM capacitor having a generally corrugated profile. The corrugated topography is provisioned using sacrificial, self-organizing materials that effectively create a pattern in response to treatment (heat or other suitable stimulus), which is transferred to a dielectric material in which the MIM capacitor is formed. The self-organizing material may be, for example, a layer of directed self-assembly material that segregates into two alternating phases in response to heat or other stimulus, wherein one of the phases then can be selectively etched with respect to the other phase to provide the desired pattern. In another example case, the self-organizing material is a layer of material that coalesces into isolated islands when heated. As will be appreciated in light of this disclosure, the disclosed techniques can be used, for example, to increase capacitance per unit area, which can be scaled by etching deeper capacitor trenches/holes.

Abstract: A transistor, a method and an apparatus for forming multiple connections to a transistor for reduced gate (FET/HEMT) or base (BJT/HBT) parasitics, and improved multi-finger transistor thermal impedance. Providing for a method and an apparatus that reduces a transistor's parasitics and reduces a transistor's thermal impedance, resulting in higher device bandwidths and higher output power. More particularly, providing for a method and an apparatus for applying compact, multiple connections to the gate of a FET (or HEMT) or the base of a BJT (or HBT) from many sides resulting in reduced parasitics and improved transistor thermal impedance.

Abstract: A semiconductor device housing package includes a base body having, on its upper surface, a mounting region of a semiconductor device; a frame body having a frame-like portion disposed on the upper surface of the base body, surrounding the mounting region, and an opening penetrating through from an inner side of the frame-like portion to an outer side thereof; a flat plate-like insulating member disposed in the opening, extending from an interior of the frame body to an exterior thereof; wiring conductors disposed on an upper surface of the insulating member, extending from the interior of the frame body to the exterior thereof; and a metallic film disposed on a part of the upper surface of the insulating member, the metallic film lying outside the frame body surrounding the wiring conductors.

Abstract: Methods and structures for thermoelectric cooling of 3D semiconductor structures are disclosed. Thermoelectric vias (TEVs) to form a thermoelectric cooling structure. The TEVs are formed with an etch process similar to that used in forming electrically active through-silicon vias (TSVs). However, the etched cavities are filled with materials that exhibit the thermoelectric effect, instead of a conductive metal as with a traditional electrically active TSV. The thermoelectric materials are arranged such that when a voltage is applied to them, the thermoelectric cooling structure carries heat away from the interior of the structure from the junction where the thermoelectric materials are electrically connected.