Abstract: A semiconductor element of this invention includes a drift layer of a first conductivity type formed on a semiconductor substrate of the first conductivity type, a well layer of a second conductivity type selectively formed in the surface of the drift layer, a source layer of the first conductivity type selectively formed in the surface of the well layer, a trench formed to reach at least the inside of the drift layer from the surface of the source layer through the well layer, a buried electrode formed in the trench through a first insulating film, and a control electrode formed on the drift layer, the well layer, and the source layer through a second insulating film.

Abstract: Multilayer anode structures (104) for electronic devices (100) such as polymer light-emitting diodes are described. The multilayer anodes include a high conductivity organic layer (114) adjacent to the photoactive layer (102) and a low conductivity organic layer (112) between the high conductivity organic layer and the anode's electrical connection layer (110). This anode structure provides polymer light emitting diodes which exhibit high brightness, high efficiency and long operating lifetime. The multilayer anode structure of this invention provides sufficiently high resistivity to avoid cross-talk in passively addressed pixellated polymer emissive displays; the multilayer anode structure of this invention simultaneously provides long lifetime for pixellated polymer emissive displays.

Abstract: An electrical resistor structure overlies a substrate and comprises a composite resistor having a first resistor of relatively low resistance and a second resistor of relatively high resistance overlying the first resistor. First and second electrodes make contact with the composite resistor at spaced locations, and a bond pad overlies the second resistor at a position between the electrodes. A metallized fiber is soldered a to a metal bond pad by providing a stacked resistor structure beneath the bond pad, disposing a solder preform over the bond pad, disposing the metallized fiber over the bond pad, and flowing a current through the stacked resistor structure. The stacked resistor structure, when subjected to a current flowing generally along a first axis, is characterized by a temperature profile that has first and second peaks on either side of the bond pad.

Abstract: An exemplary method for fabricating a thin film transistor array substrate (200) includes: providing an insulating substrate (201); coating a transparent conductive layer (202) and a gate metal layer (203) on the substrate; forming a gate electrode (213) and a pixel electrode (212) using a first photo-mask process; forming a gate insulating layer (204), an amorphous silicon layer (205), a doped amorphous silicon layer (206), and a source/drain metal layer (207) on the substrate; forming a plurality of source electrodes (227) and a plurality of drain electrodes (228) using a second photo-mask process; depositing a metal layer (208) on the substrate and the pixel electrodes; and forming a passivation layer (209) on the source electrodes, the drain electrodes and the channels and a plurality of metal contact layers (218) using a third photo-mask process.

Abstract: A light sensor located above an integrated circuit including a lower electrode, a heavily-doped amorphous silicon layer of a first conductivity type, and a lightly-doped amorphous silicon layer of a second conductivity type. The lightly-doped amorphous silicon layer rests on a planar surface at least above and in the vicinity of the lower electrode.

Abstract: A method of manufacturing a thin film transistor (TFT) which is manufactured such that source and drain electrodes directly contact source and drain regions without contact holes.

Abstract: A nitride-based semiconductor light-emitting device capable of improving luminous efficiency by reducing light absorption loss in a contact layer is provided. This nitride-based semiconductor light-emitting device comprises a first conductivity type first nitride-based semiconductor layer formed on a substrate, an active layer, formed on the first nitride-based semiconductor layer, consisting of a nitride-based semiconductor layer, a second conductivity type second nitride-based semiconductor layer formed on the active layer, an undoped contact layer formed on the second nitride-based semiconductor layer and an electrode formed on the undoped contact layer.

Abstract: An accumulation mode FET (ACCUFET) which includes an insulated gate, an adjacently disposed insulated source field electrode, and a source contact that makes Schottky contact with the base region of the ACCUFET.

Abstract: In a liquid crystal display device, liquid crystal molecules are oriented in a vertical direction to the first substrate and the second substrate by the first molecule orientation film and the second molecule orientation film, respectively, in a non-driving state. A structural pattern is formed so as to extend in a first direction parallel to a surface of the liquid crystal layer and so as to form, in a driving state, an electric field periodically changing in a second direction that is parallel to the liquid crystal layer and vertical to the first direction. The liquid crystal molecules substantially tilt in the first direction in the driving state.

Abstract: Methods of forming a self-aligned, selective semiconductor on insulator (SOI) structure and a related structure are disclosed. In one embodiment, a method includes providing a substrate; forming a gate structure over a channel within the substrate; recessing a portion of the substrate adjacent the channel; forming an insulating layer on a bottom of the recessed portion; and forming a semiconductor material above the insulating layer. An upper surface of the semiconductor material may be sloped. A MOSFET structure may include a substrate; a channel; a source region and a drain region adjacent the channel; a gate structure above the channel and the substrate; a shallow trench isolation (STI) distal from the gate structure; a selectively laid insulating layer in at least one of the source region and the drain region; and an epitaxially grown semiconductor material above the selectively laid insulating layer.

Abstract: A TFT of the present invention includes a gate electrode, a gate insulating film and a first semiconductor film which are sequentially formed on an insulating substrate, a second semiconductor film including a high density impurity which is formed on the first semiconductor film while being separated into portions at grade and a first electrode and a second electrode, each of which is formed on the separated second semiconductor film. Further, a peripheral portion of the first semiconductor film includes a protruded portion toward the outside from an edge of the second semiconductor film, and a surface of the protruded portion is roughened. By roughening the surface of the protruded portion, an on-current of the TFT can be maintained and the leakage current can be suppressed.

Abstract: A crystalline semiconductor film in which the position and size of a crystal grain is controlled is fabricated, and the crystalline semiconductor film is used for a channel formation region of a TFT, so that a high performance TFT is realized. An island-like semiconductor layer is made to have a temperature distribution, and a region where temperature change is gentle is provided to control the nucleus generation speed and nucleus generation density, so that the crystal grain is enlarged. In a region where an island-like semiconductor layer 1003 overlaps with a base film 1002, a thick portion is formed in the base film 1002. The volume of this portion increases and heat capacity becomes large, so that a cycle of temperature change by irradiation of a pulse laser beam to the island-like semiconductor layer becomes gentle (as compared with other thin portion).

Abstract: Method and system for providing a dynamically reconfigurable display having nanometer-scale resolution, using a patterned array of multi-wall carbon nanotube (MWCNT) clusters. A diode, phosphor or other light source on each MWCNT cluster is independently activated, and different color light sources (e.g., red, green, blue, grey scale, infrared) can be mixed if desired. Resolution is estimated to be 40-100 nm, and reconfiguration time for each MWCNT cluster is no greater than one microsecond.

Abstract: A method for fabricating heterojunction field effect transistors (HFET) and a family of HFET layer structures are presented. In the method, a step of depositing a HFET semiconductor structure onto a substrate is performed. Next, a photoresist material is deposited. Portions of the photoresist material are removed corresponding to source and drain pad pairs. A metal layer is deposited onto the structure, forming source pad and drain pad pairs. The photoresist material is removed, exposing the structure in areas other than the source and drain pad pairs. Each source and drain pad pair has a corresponding exposed area. The structure is annealed and devices are electrically isolated. The exposed area of each device is etched to form a gate recess and a gate structure is formed in the recess. Semiconductor layer structures for GaN/AlGaN HFETs are also presented.

Abstract: A thin film transistor, and a flat panel display with the same, including a gate electrode, source and drain electrodes, an organic semiconductor layer, and a gate insulating layer. A first capacitance is a capacitance at a first point where the organic semiconductor layer, an electrode, and the gate insulating layer contact one another, a second capacitance is a capacitance at a second point where the organic semiconductor layer contacts the gate insulating layer, a third capacitance is a capacitance at a third point where the electrode contacts the gate insulating layer, and a fourth capacitance is a capacitance at a fourth point where the organic semiconductor layer contacts the electrode. The first capacitance is greater than one of the second capacitance, the third capacitance, and the fourth capacitance.

Abstract: A first semiconductor light emitting device includes: a transparent substrate; a light emitting layer; and a roughened region. The transparent substrate has a first major surface and a second major surface, and is translucent to light in a first wavelength band. The light emitting layer is selectively provided in a first portion on the first major surface of the transparent substrate and configured to emit light in the first wavelength band. The roughened region is provided in a second portion different from the first portion on the first major surface. A second semiconductor light emitting device includes: a transparent substrate; a light emitting layer; a first electrode; and at least one groove. The groove is provided on the second major surface of the transparent substrate and extends from a first side face to a second side face opposing the first side face of the transparent substrate.

Abstract: The temperature of a bipolar semiconductor element using a wide-gap semiconductor is raised using heating means, such as a heater, to obtain a power semiconductor device being large in controllable current and low in loss. The temperature is set at a temperature higher than the temperature at which the decrement of the steady loss of the wide-gap bipolar semiconductor element corresponding to the decrement of the built-in voltage lowering depending on the temperature rising of the wide-gap bipolar semiconductor element is larger than the increment of the steady loss corresponding to the increment of the ON resistance increasing depending on the temperature rising.

Abstract: A semiconductor device includes: a SOI substrate having a SOI layer, a buried oxide layer and a support substrate; multiple first separation trenches on the SOI layer; multiple MOS transistors, each of which is surrounded with one first separation trench; a second separation trench on the SOI layer including n-ply field trenches; and multiple field regions such that a k-th field region is surrounded with a k-th field trench. One MOS transistor is disposed in each field region. The MOS transistors are connected in series. The first MOS transistor has a gate terminal as an input terminal. The n-th MOS transistor is connected to the power source potential through an output resistor. The n-th field region has an electric potential, which is fixed to the power source potential.

Abstract: The temperature of a bipolar semiconductor element using a wide-gap semiconductor is raised using heating means, such as a heater, to obtain a power semiconductor device being large in controllable current and low in loss. The temperature is set at a temperature higher than the temperature at which the decrement of the steady loss of the wide-gap bipolar semiconductor element corresponding to the decrement of the built-in voltage lowering depending on the temperature rising of the wide-gap bipolar semiconductor element is larger than the increment of the steady loss corresponding to the increment of the ON resistance increasing depending on the temperature rising.

Abstract: A nitride-based light emitting device having a light emitting layer between an N-type clad layer and a P-type clad layer is provided. The light emitting device including: a reflective layer which reflects light emitting from the light emitting layer; and at least one metal layer which is formed between the reflective layer and the P-type clad layer.